Electrostatic discharge protection circuit and semiconductor...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Reexamination Certificate

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07852608

ABSTRACT:
An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDD1is applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDD1and VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDD1and VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.

REFERENCES:
patent: 5515232 (1996-05-01), Fukazawa et al.
patent: 2001/0043449 (2001-11-01), Okushima
patent: 2006/0114047 (2006-06-01), Irino
patent: 2006/0125514 (2006-06-01), Hashimoto
Patent Abstract of Japan, Japanese Publication No. 09-036245, Published Feb. 7, 1997.
Patent Abstract of Japan, Japanese Publication No. 2006-121007, Published May 11, 2006.
Patent Abstract of Japan, Japanese Publication No. 11-220031, Published Aug. 10, 1999.
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Patent Abstract of Japan, Japanese Publication No. 2005-285160, Published Oct. 13, 2005.
Patent Abstract of Japan, Japanese Publication No. 2004-336800, Published Nov. 25, 2004.

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