Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2006-09-05
2006-09-05
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
07102862
ABSTRACT:
Circuits are disclosed for protecting internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge (EDS). One example circuit includes a trigger circuit including a transistor and a capacitor arranged in series between DC pads. The trigger circuit generates a trigger signal to a discharge circuit connected between the DC pads to shunt charge from one of the DC pads to the other. The RC delay associated with the transistor and capacitor of the trigger circuit may be designed such that the trigger circuit generates the trigger signal in response to an ESD event, but not in response to high positive spikes on one of the DC pads during normal operation.
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Lien Chuen-Der
Tien Ta-Ke
Benenson Boris
Finnegan & Henderson et al.
Integrated Device Technology Inc.
Sircus Brian
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