Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2001-11-20

2004-06-01

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C361S091100, C361S058000

Reexamination Certificate

active

06744610

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90111022, filed May 9, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electronic circuit. More particularly, the present invention relates to an electrostatic discharge (ESD) protection circuit.
2. Description of Related Art
The electrostatic discharge is one of the major causes that damage an integrated circuit (IC), such as an dynamic random access memory (DRAM) or an statistic random access memory (SRAM), during or after the manufacturing process. Therefore, an electrostatic discharge protection circuit is usually made as a part of the circuit to prevent damage on the integrated circuit caused by external electrostatic. The issue of ESD robustness has been reported in the book “ESD IN SILICON INTEGRATED CIRCUIT” by AJITH AMERASEKERA& CHARVAKA DUVVURY, published by John Wiley & Sons.
FIG. 1
illustrates a conventional design of an electrostatic discharge protection circuit. In
FIG. 1
, the electrostatic discharge protection circuit includes a transistor
50
and an N-type metal-oxide semiconductor (NMOS)
52
. A source/drain region of the PMOS transistor
50
is connected to a system power source and another source/drain region is connected to the bonding pad
54
. A gate electrode of the PMOS transistor
50
is connected to a pre-stage driver
61
. The connected source/drain regions of the NMOS transistor
52
and the PMOS transistor
50
are connected to the bonding pad
54
. The gate electrode of the NMOS transistor
52
is connected to a pre-stage driver
60
. Another source/drain region of the NMOS transistor
52
is connected to a ground voltage. In this kind of electrostatic discharge protection circuit as shown in
FIG. 1
, an parasitic capacitor
56
exists between the gate electrode and the source/drain region of the NMOS transistor
52
. When an electrostatic pulse enters from the bonding pad
54
, it will bring up the voltage of the gate electrode of the NMOS transistor
52
due to the effect of the parasitic capacitor
56
. Then, a snap-back voltage of the NMOS transistor
52
is reduced. As a result, the electrostatic charges can flow to the ground through the NMOS transistor
52
. If there is no the parasitic capacitor
56
to bring up the voltage of the gate electrode of the NMOS transistor
52
, the snap-back voltage of the NMOS transistor
52
will be higher, and therefore the protection capability of the NMOS transistor
52
is reduced. Another conventional design of the electrostatic discharge protection circuit used for over voltage tolerant I/O pad is illustrated in FIG.
2
. In
FIG. 2
, the electrostatic discharge protection circuit includes two NMOS transistors
50
,
52
. A source/drain region of the NMOS transistor
50
is connected to a bonding pad
54
. The gate electrode of the NMOS transistor
50
is connected to a system power source. Another source/drain region of the NMOS transistor
50
is connected to a source/drain region of the NMOS transistor
52
. The gate electrode of the NMOS transistor
52
is connected to a pre-stage driver
60
. When the electrostatic charges enter from the bonding pad
54
, the charges have a longer path to flow to the ground and it has no effective parasitic capacitor to bring up the voltage of the gate electrode of the NMOS transistor in order to reduce the snap-back voltage. In this circuit, the protection capability for the electrostatic charge is far worse than the circuit of FIG.
1
.
SUMMARY OF THE INVENTION
The invention provides an electrostatic discharge protection circuit. It includes a capacitor loop for improving the protection on the circuit.
As embodied and broadly described herein, the invention provides an electrostatic discharge protection circuit and is connected between a bonding pad and a pre-stage driver. The electrostatic discharge protection circuit includes a PMOS transistor and a NMOS transistor connected in the series. A source/drain region of the PMOS transistor is connected to a system power source Vcc. And the gate electrode is connected to a pre-stage driver. The other source/drain region of the PMOS transistor is connected to a source/drain region of the NMOS transistor, which is also connected to the bonding pad. The other source/drain region of the NMOS transistor is connected to the ground. The gate electrode of the NMOS transistor receives the output of the pre-stage driver. For the PMOS transistor, a capacitor is connected between a source/drain region connected to system power source Vcc and the gate electrode of the NMOS transistor.
From the above, the loop capacitor, through parasitic diode
58
, in parallel with parasitic capacitor
56
to bring up the gate voltage of NMOS transistor
52
where an ESD pulse entering from bonding pad. Thus, a more effective and stable electrostatic discharge protection circuit that can sustain a large electrostatic voltage is provided.
As embodied and broadly described herein, the invention provides the other electrostatic discharge protection circuit and is connected between a bonding pad and a pre-stage device. This electrostatic discharge protection circuit includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a capacitor and a second PMOS transistor. The first PMOS transistor includes a first source/drain region, a second source/drain region and a gate electrode. The first source/drain of the first PMOS transistor is connected to a system power source, and the gate electrode is connected to a pre-stage driver. The second source/drain is connected to the bonding pad. A first NMOS transistor includes a first source/drain region, a second source/drain region and a gate electrode. The first source/drain region of the first NMOS transistor is connected to the bonding pad, and the gate electrode is connected to the system power source. A second NMOS transistor includes a first source/drain region, a second source/drain region and a gate electrode. The first source/drain region of the second NMOS transistor is connected to the second source/drain region of the first NMOS transistor. The second source/drain region of the second NMOS transistor is grounded, and the gate electrode of the second NMOS transistor receives the output of the pre-stage driver. The capacitor includes a first source/drain, a second source/drain region and a gate electrode. The capacitor connects between the first source/drain region of the second PMOS transistor and the substrate of the first PMOS transistor. The gate electrode of the second PMOS transistor is connected to the system power source. The second source/drain region of the second PMOS transistor is connected to the gate electrode of the second NMOS transistor and receives the output of the pre-stage driver.
In above description, the capacitor includes a metal-oxide semiconductor capacitor. The pre-stage device includes a pre-stage driver.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5631793 (1997-05-01), Ker et al.
patent: 5892262 (1999-04-01), Wu et al.
patent: 6388850 (2002-05-01), Ker et al.
patent: 6538868 (2003-03-01), Chang et al.

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