Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2001-12-28

2004-12-07

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06829126

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit in a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1
shows an electrostatic discharge (hereinafter abbreviated “ESD”) protection circuit constructed with NMOS transistors according to a related art.
Referring to
FIG. 1
, a drain of an NMOS transistor N
1
is connected to a pad (input or output)
10
and a source is connected to a ground Vss
2
. A gate is connected to a ground Vss
1
when used for an ESD protection circuit or to a pull-down inverter when used for a driving transistor.
The NMOS transistor N
1
includes a parasitic bipolar transistor B
1
. The parasitic bipolar transistor B
1
is constructed with a collector/emitter as the drain/source of the NMOS transistor N
1
and a base as a substrate of the NMOS transistor N
1
. In this case, the base is connected to the ground Vss
2
.
The pad
10
is connected to an internal circuit
12
through a resistance R. Between one end of the resistance R and the ground Vss
2
, an NMOS transistor N
2
is located. The NMOS transistor N
2
includes another parasitic bipolar transistor of which the gate and source are connected to each other. In this case, the resistance R reduces an ESD current flowing to the NMOS transistor N
2
, and the NMOS transistor N
2
removes ESD stress still remaining after removal by the NMOS transistor N
1
.
FIG. 2
shows a layout of an ESD protection circuit in FIG.
1
.
Operation of the above-constructed ESD protection circuit of the related art is explained as follows.
Referring to
FIG. 2
, when ESD stress is applied to the pad, a high voltage is applied to the drain of the NMOS transistor N
1
. If the high voltage is applied to the drain, holes are discharged to the substrate by junction breakdown between a source region n+ and the substrate p+. In this case, electrons of the source migrate to the drain if the hole current enables a breakdown voltage high enough to overcome a potential barrier of 0.7V between the n+ source region and the p+ substrate. If the potential barrier is overcome, the transistor B
1
is turned on, and the required voltage is called a triggering voltage.
The triggering voltage of the NMOS transistor N
1
is about 7V in submicrontechnology. Thus, the triggering voltage becomes higher than the breakdown voltage (~5.5V) of a gate insulating layer of the NMOS transistor. This relationship of the triggering voltage exceeding the breakdown voltage causes damage on the gate insulating layer of the NMOS transistor N
1
in the related art.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an ESD protection circuit that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an ESD protection circuit enabling to increase ESD immunity of semiconductor devices.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an ESD protection circuit includes an NMOS transistor connected between an input/output pad and a ground, the NMOS transistor having a parasitic bipolar transistor, and at least one diode connected between the input/output pad and the NMOS transistor.
In another aspect of the present invention, an ESD protection circuit includes an input/output pad; a plurality of N diodes connected in series between the input/output pad and a substrate of an NMOS transistor wherein the NMOS transistor is connected between the input/output pad and the substrate and has a parasitic bipolar transistor connected to plurality of N the diodes.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 4795918 (1989-01-01), Menon et al.
patent: 5814865 (1998-09-01), Duvvury et al.
patent: 5946177 (1999-08-01), Miller et al.
patent: 6292343 (2001-09-01), Pequignot et al.
patent: 6399990 (2002-06-01), Brennan et al.
patent: 6437407 (2002-08-01), Ker et al.
patent: 6501632 (2002-12-01), Avery et al.
patent: 6529359 (2003-03-01), Verhaege et al.

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