Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

1993-09-17

1996-05-28

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 257358, H01L 2362, H02H 904

Patent

active

055217834

ABSTRACT:
An electrostatic discharge (ESD) protection circuit formed on a semiconductor substrate includes a first stage clamping circuit and a second stage clamping circuit separated by a dissipative circuit. The first and second stage clamping circuits are designed to absorb and dissipate the high and low energy ESD, respectively. The first clamping circuit has a self-regulated current mechanism capable of diverting the electrical current generated by an ESD from a high current density region to a low current density region within the semiconductor substrate, and simultaneously lowers the ESD induced voltage for safe protection.

REFERENCES:
patent: 4567500 (1986-01-01), Avery
patent: 4605980 (1986-08-01), Hartranft et al.
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 5051860 (1991-09-01), Lee et al.
patent: 5335134 (1994-08-01), Stein et al.
Analog Devices Data Sheet: AD892E/AD892T, Apr. 1990.

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