Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2000-03-23

2002-02-26

Patel, Rajnikant B. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C257S355000

Reexamination Certificate

active

06351364

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89104921, filed Mar. 17, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an ESD protection circuit, of which the parasitic bipolar junction transistor (BJT) can be turned on in advance by triggering a substrate under ESD stress conditions, so that the ESD capacity can be enhanced.
2. Description of the Related Art
Electrostatic discharge (ESD) can easily damage IC devices such as DRAMs and SRAMs during both manufacture and operation. A person walking on a carpet, for instance, can carry up to several thousand volts of electrostatic charge under high relative humidity (RH) conditions and over 10,000 volts under low RH conditions. If such a person touches an IC package, the electrostatic charge on his/her body is instantly discharged to the IC package, thus causing ESD damage to the internal circuitry of the IC package. A widely used solution to this problem is to provide an on-chip ESD protection circuit around each I/O pad of the IC package.
One drawback to the prior art, however, is that when the IC device is fabricated by scaled down technology, such as the deep-submicron CMOS process, the gate-oxide structure is reduced in thickness. This causes the breakdown voltage of the gate-oxide structure to be close to or below the breakdown voltage at the source/drain junction, thus degrading the ESD protection capability. The internal circuitry of an IC device is typically drawn in accordance with the Minimum Design Rules. Therefore, the various semiconductor components of an IC device are designed to have the minimum size. This practice, however, makes some components vulnerable to ESD stress when these components are further scaled down. For this reason, a highly integrated IC device fabricated by deep-submicron process is particularly vulnerable to ESD. Therefore, in the IC industry, much research effort has been directed to ESD protection for integrated circuitry.
FIG. 1
is a circuit diagram for a conventional cascode ESD protection circuit disposed between an I/O pad
10
and an internal circuit
12
. As shown in
FIG. 1
, the conventional cascode ESD protection circuit comprises two NMOS transistors
14
and
16
and a PMOS transistor
18
.
According to the circuit structure in
FIG. 1
, though the NMOS transistor
14
and
16
connected in serial can enhance the reliability, the drain-source voltage Vds of NMOS transistor
14
and
16
will be decreased and the drain junction avalanche effect will get worse due to the result of bias voltage and the effect of coupling voltage, thus the ESD protection ability will get worse than the conventional gated P-N structure. Additionally, the reason for turning on the parasitic bipolar junction transistor
20
between the drain of NMOS transistor
14
and the source of NMOS transistor
16
is the trigger voltage must be increased (that is, the snapback trigger voltage increased), as a result, the ESD protection ability will be reduced.
Therefore, in a mixed I/O circuit, how to improve the reliability and the ESD protection ability simultaneously for a cascode circuit is very important.
SUMMARY OF THE INVENTION
The invention provides an electrostatic discharge (ESD) protection circuit disposed between an I/O pad and an internal circuit. The ESD protection circuit comprises three NMOS transistors and two PMOS transistors. A first NMOS transistor has a drain terminal connected to the I/O pad and a gate terminal connected to a voltage source. A second NMOS transistor has a drain terminal connected to a source terminal of the first NMOS transistor and a source and a gate terminal connected to a ground voltage. A third NMOS transistor has a source terminal connected to the I/O pad, a drain terminal connected to the voltage source and a gate and a substrate terminal connected to the ground voltage. A first PMOS transistor has a drain terminal connected to the ground voltage and a substrate terminal of the second NMOS transistor, a source and a substrate terminal connected to the I/O pad and a gate terminal connected to the voltage source. And, a second PMOS transistor has a source and a gate terminal connected to the voltage source, a drain terminal connected to the I/O pad and a substrate terminal connected to a drain terminal of the third NMOS transistor. Furthermore, the ESD protection circuit of the invention further comprises a first resistor and a second resistor, wherein the first resistor is disposed between the drain terminal of the first PMOS transistor and the ground voltage, and the second resistor is disposed between the drain terminal of the three NMOS transistor and the voltage source.
According to the ESD protection circuit of the invention, whether a positive voltage stress is applied to ground voltage VSS or a negative voltage stress is applied to voltage source VDD, both the parasitic BJT of the second NMOS transistor and the second PMOS transistor can be turned on in advance by triggering the junctions between their substrates and sources, and the ESD stress then can be discharged to the ground voltage VSS and the voltage source VDD, so that the capacity of the ESD protection circuit in this invention is thus improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5361185 (1994-11-01), Yu
patent: 5905614 (1999-05-01), Colombo
patent: 6091594 (2000-07-01), Williamson et al.

Affiliated with

Also associated with

Rating

Electrostatic discharge protection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2981985