Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2000-06-02

2002-11-12

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257S347000, C257S355000, C257S357000, C257S369000

Reexamination Certificate

active

06479883

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89207377, filed May 4, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electrostatic discharge protection circuit. More particularly, the present invention relates to a MOSFET having a tunnel source-body contact device that can be applied to a silicon-no-insulation (SOI) substrate.
2. Description of Related Art
Electrostatic discharge is one of the leading causes of damage to integrated circuits(IC) such as dynamic random access memory (DRAM) and static random access memory (SRAM) during manufacturing and post-manufacture transportation. For example, a person walking on carpet in a high relative humidity environment can generate several hundred to several thousand volts of static electricity. Under exceptionally dry conditions, up to ten thousand volts may be generated. When a charged body comes into contact with a silicon chip, static electricity may discharge, causing irreparable damages to the chip. To minimize damages to the chip due to electrostatic discharge, hard-wired electrostatic discharge circuits are often provided. In other words, an on-chip electrostatic discharge protection circuit is formed between the internal circuit and each bonding pad.
FIG. 1
is a circuit diagram of a conventional electrostatic discharge protection circuit. As shown in
FIG. 1
, the electrostatic discharge protection circuit is formed between the input/output pad
10
and the internal circuit
12
. Any excess voltage applied to the input/output pad
10
is discharged so that a suitable range of voltage is input into the internal circuit
12
. The electrostatic discharge circuit includes a PMOS transistor
14
and an NMOS transistor
16
. The source terminal of the PMOS transistor
14
is connected to a voltage Vdd. The gate terminal and the source terminal of the PMOS transistor
14
are connected together. The drain terminal of the NMOS transistor
16
is connected to the drain terminal of the PMOS transistor
14
. The drain terminal of the NMOS transistor
16
and the drain terminal of the PMOS transistor
14
are connected to a junction point
18
between the input/output pad
10
and the internal circuit
12
. Both the gate terminal and the source terminal of the NMOS transistor
16
are connected to an earth voltage Vss.
The bulk electrostatic discharge protection circuit as shown in
FIG. 1
has a gated N-P structure. Hence, the substrate portion of the PMOS transistor
14
and the NMOS transistor
16
are connected to the respective source terminals, which are in turn connected to a source voltage Vdd and an earth voltage Vss, respectively. Consequently, a parasitic diode
20
is formed between the PMOS transistor
14
and the junction point
18
. Similarly, a parasitic diode
22
is formed between the NMOS transistor
16
and the junction point
18
. In other words, parasitic diodes are formed at the junction between the drain terminals and the substrate. When the input/output pad
10
is subjected to an excessive negative voltage, the parasitic diode
22
conducts so that a discharge path from an input/output pad
10
to earth voltage Vss for the negative stress is provided. On the other hand, when the input/output pad
10
is subjected to an excessive positive voltage, the parasitic diode
20
conducts so that a discharge path from an input/output pad
10
to voltage Vdd for the positive stress is provided.
As techniques for manufacturing sub-micron devices have matured, a silicon-on-insulator (SOI) type of CMOS has emerged. In SOI technology, a layer of insulator is formed not too far from the surface of a silicon substrate so that the substrate surface of the CMOS device is separated from the silicon bulk. Hence, the source terminal and the substrate will not latch with the well and substrate material. In other words, the gated N-P structure shown in
FIG. 1
is unsuitable for SOI CMOS. This is because the SOI device is a three-terminal device, while the electrostatic discharge protection circuit device is a four-terminal device. When SOI CMOS is used as an electrostatic discharge protection circuit, no parasitic diodes are formed at the junction between the drain terminal and the substrate. Since the capacity to eliminate positive or negative stress is lost, the electrostatic discharge circuit no longer functions.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an electrostatic discharge protection circuit suitable for protecting SOI CMOS.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an electrostatic discharge protection circuit. The protection circuit is formed between an input/output pad and an internal circuit. The protection circuit includes two n-type tunneling source-body contact devices connected in a series. The drain terminal of the first n-type tunneling source-body contact device is connected to a high voltage. The gate terminal of the first n-type tunneling source-body contact device is also connected to the source terminal. The source terminal of the first n-type tunneling source-body contact device is connected to a junction point between the input/output pad and the internal circuit. The drain terminal of the second n-type tunneling source-body contact device is connected to the source terminal of the first n-type tunneling source-body contact device. Both the gate terminal and the source terminal of the second n-type tunneling source-body contact device are connected to a low voltage.
The first and the second n-type tunneling source-body contact device structurally comprise of a substrate layer, an insulation layer, a drain region, a p+ region, a p-well region, a source region, a gate region and two sidewall spacers. The substrate layer is at the bottom with the insulation layer on top to form an SOI basic structure. The source region, the p+ region, the p-well region and the drain region are formed above the insulation layer in such a way that they are sequentially connected. The gate region is formed above a portion of the p-well region. Finally, spacers are formed on the sidewalls of the gate region above a portion of the p-well region, the drain region and the source region.
The substrate layer can be a p-type layer, and the insulation layer can be a silicon dioxide layer, for example. In addition, a metallic layer can be deposited over the drain region, the source region and the gate region for connecting to a plurality of external voltages. In general, the low voltage is obtained by connecting to an earth voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5321293 (1994-06-01), Mojaradi et al.
patent: 5608340 (1997-03-01), Shibata et al.
patent: 5844272 (1998-12-01), Soderbarg et al.
patent: 5880620 (1999-03-01), Gitlin et al.
patent: 6274908 (2001-08-01), Yamaguchi et al.

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