Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

1988-06-27

1991-04-30

Hille, Rolf

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 13, 357 43, 357 51, 361 56, H01L 29740, H01L 29900, H01L 2720, H02H 900

Patent

active

050123173

ABSTRACT:
An ESD protection device includes a PNPN type device disposed between the input pad (12) and ground. A first P-layer (48) is disposed in an N-type well (46) which is formed in a P-type layer (44). A second N-region (52) is provided for connection to ground. This provides an SCR which can be turned on by avalanching the intermediate PN junction (32) to place the device in a regenerative mode for positive transients. For negative transients, a P+ region (54) is provided in P-layer (44) to bypass a PN junction (34) and a N+ region (50) is defined in the N-type region (46) to bypass PN junction (30). This provides a forward-biased diode for the negative transient.

REFERENCES:
patent: 2655610 (1953-10-01), Ebers
patent: 4117507 (1978-09-01), Pacor
patent: 4282555 (1987-08-01), Suedberg
patent: 4400711 (1983-08-01), Avery
patent: 4484244 (1984-11-01), Avery
patent: 4605872 (1986-08-01), Rung
patent: 4626882 (1986-12-01), Cottrell et al.
Using SLR's as Transient Protection Structure in Integrated Circuits L. R. Avery RCA DSRC EOS/ESD Symposium Proceedings, 1983, pp. 177-180.
Rountree et al., "A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes," 1988 EOS/ESD Symposium.

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