Electrostatic discharge protection apparatus

Details Electrostatic discharge protection apparatus Electrostatic discharge protection apparatus

2000-07-12

2002-11-05

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000, C361S118000

Reexamination Certificate

active

06477023

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an electrostatic discharge (ESD) protection apparatus. More particularly, this invention relates to a layout of an electrostatic discharge apparatus that occupies a greatly reduced area compared to the area occupied by the conventional electrostatic discharge protection apparatus.
2. Description of the Related Art
In a fabrication process of an integrated circuit (IC) such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or after the chip is fabricated, the electrostatic discharge is the major cause to damage the integrated circuit. For example, when a human being walking on a blanket, in an environment with a high relative humidity (HR), the human being may carry from hundreds to thousands of electrostatic voltages. When the relative humidity is low, more than ten thousand of electrostatic voltages may be carried. In case the carried electrostatic charges are in contact with the chip, the chip is easily damaged to malfunction. To avoid the electrostatic discharge damage, various electrostatic protection methods or apparatus are developed. A very common type of electrostatic protection is to design an on-chip electrostatic discharge protection circuit between the internal circuit and each pad.
However, as the size of the integrated circuits reduces as the increase of the integration, the breakdown voltage of the gate oxide is approaching the junction breakdown voltage of the source/drain region, or even lower. The performance of the electrostatic discharge protection circuit is thus greatly deteriorated. In addition, the internal circuit is typically designed according to the minimum design rules without a proper design to withstand a huge electrostatic discharge transient current. For example, the space between the contact window and the edge diffusion region and between the contact window and the edge of the gate is designed insufficiently large. Under a high integration, the chip is easily to be damaged by the electrostatic discharge. Therefore, the electrostatic discharge has become a major cause to damage the deep sub-micron integrated circuit.
In addition to the consideration of the performance in electrostatic discharge protection, to increase the density of circuit layout, that is, to form the electrostatic discharge protection apparatus in a smaller area is also an important topic for modern integrated circuit design.
SUMMARY OF THE INVENTION
The invention provides an electrostatic discharge (ESD) protection circuit layout comprising a pad, a drain region, a gate and a source region. The drain region is located under the pad. The gate is formed at a periphery of the pad. The source region is located to surround the gate.
The electrostatic discharge protection apparatus provided by the invention comprises a pad, a drain region, multiple gates and multiple source regions. The drain region is located under the pad. The gates are surrounding the pad. Each source region is formed at a periphery of a corresponding gate.
The invention further provides another electrostatic discharge protection apparatus that comprises pads, a P-type drain region, an N-type drain region, a first gate, a second gate, a P-type source region and an N-type source region. The P-type drain region and the N-type drain region are located under the pad. The first gate is located at a periphery of a pad corresponding to the P-type drain region. The P-type source region is surrounding the first gate and the N-type source region is surrounding the second gate.
Thus design, the area of the wafer used for forming the electrostatic discharge protection is greatly reduced. It is thus applicable for devices with a more compact structure, such as the integrated circuit with a linewidth of deep submicron.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4807080 (1989-02-01), Clark
patent: 4855257 (1989-08-01), Kouda

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