Electrostatic discharge protecting circuit for semiconductor...

Details Electrostatic discharge protecting circuit for semiconductor... Electrostatic discharge protecting circuit for semiconductor...

1999-12-10

2002-02-05

Ballato, Josei (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C361S090000, C361S091100, C361S117000

Reexamination Certificate

active

06344960

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge protecting circuit for a semiconductor device, and more particularly to an electrostatic discharge protecting circuit for a semiconductor device in which when an electrostatic discharge signal is applied from an external source through a pad, bulk terminal of an N-type MOS transistor used for an electrostatic discharge protecting circuit is connected to a ground voltage, to thereby improve the electrostatic discharging characteristics.
2. Description of the Background Art
FIG. 1
is a block diagram of a conventional semiconductor device including an electrostatic discharge protecting circuit, which shows a part related to an input/output pad peripheral circuit and an electrostatic discharge protecting circuit in the semiconductor device, including a first block
1
for serving as an output buffer under the control of a first and a second control signals CON
1
and CON
2
when it performs a normal memory operation upon being connected to an internal circuit, and serving as an electrostatic discharge protecting circuit when it performs an evaluation of electrostatic discharge characteristics; a pad
2
for receiving an electrostatic discharge signal ESDS; a second block for serving as an electrostatic discharge protecting circuit according to the electrostatic discharge signal ESDS inputted to the pad
2
; and an internal circuit
4
(i.e., an input buffer) for receiving an output signal from the first block
1
as inputted to the pad
2
.
The first block
1
includes a first PMOS transistor PM
11
, connected in serial to a power supply voltage VCC and a ground voltage VSS, having a gate to which a first control signal CON
1
is applied and a bulk commonly connected to a source thereof to which a power supply voltage VCC is applied; and a first NMOS transistor NM
11
, connected in serial to the power supply voltage VCC and a ground voltage VSS, having a gate to which a second control signal CON
2
is applied, a bulk to which a back bias voltage VCC is applied or floated and a source connected to the ground voltage VSS. A drain commonly connected to the first PMOS transistor PM
11
and the first NMOS transistor NM
11
acts as an output terminal.
The second block
3
includes a second PMOS transistor PM
12
, connected in serial between a power supply voltage VCC and a ground voltage VSS and a gate, having a gate, a source and a bulk commonly connected to which the power supply voltage VCC is applied; and a second NMOS transistor, connected in serial between the power supply voltage VCC and the ground voltage VSS, having a gate and a source commonly connected to be connected to the ground power source VSS and a bulk to which a back bias voltage VBB is applied or floated. A drain commonly connected to the second PMOS transistor and a NMOS transistor acts as an input terminal and an output terminal.
An operation of the conventional electrostatic discharge protecting circuit for a semiconductor device as constructed above will now be described.
When the above-described circuit is connected to an internal circuit to perform a normal operation, the first block
1
works as a buffer. That is, the first control signal CON
1
applied to the gate of the first PMOS transistor PM
11
turns a pull-up signal PUP, the second control signal CON
2
applied to the gate of the first NMOS transistor NM
11
turns a pull-down signal PDN, and the back bias voltage VBB is applied to the bulk of the first NMOS transistor. At this time, the transistors PM
12
and NM
12
of the second block
3
are turned off not to be operated.
Meanwhile, in order to evaluate electrostatic discharge characteristics, in general, a terminal of the ground voltage VSS is connected to a ground GND and a higher voltage than the power supply voltage VCC and a lower voltage than a minus power supply voltage −VCC are respectively applied to a pad
2
. And then, after a power supply voltage terminal is connected to the ground GND, a high voltage than the power supply voltage VCC and a lower voltage than the minus power supply voltage −VCC are respectively applied to the pad
2
.
Regarding the conventional electrostatic discharge protecting circuit of
FIG. 1
, when it is performed to evaluate the electrostatic discharge characteristics, the first block
1
works as the electrostatic discharge protecting circuit. That is, the gates of the first PMOS transistor
11
and the first NMOS transistor NM
11
are floated, and the bulk of the first NMOS transistor NM
11
is also floated.
In detail, when the ground voltage VSS terminal is connected to the ground GND and an electrostatic discharge signals ESDS, that is, the higher voltage than the power supply voltage VCC and the lower voltage than the minus power supply voltage−VCC, are respectively applied to the pad
2
, the electrostatic discharge signal ESCS is discharged to the ground voltage VSS terminal by an operation of the N-P-N parasitic bipolar transistor of the first and the second NMOS transistors NM
11
and NM
12
.
And, when the power supply voltage (VCC) terminal is connected to the ground and the electrostatic discharge signals ESDS, that is, the higher voltage than the power supply voltage VCC and the lower voltage than the minus power supply voltage −VCC, are respectively applied to the pad
2
, the electrostatic discharge signal ESDS is discharged to the power supply voltage VCC terminal by a forward direction operation of a P+N-well parasitic diode existing between the first and the second PMOS transistors PM
11
and PM
12
and a P-type substrate and N-well and a parasitic bipolar transistor of the first and the second PMOS transistors PM
11
and PM
12
.
In this connection, in order to be evaluated as a normal product, a leak current caused by the electrostatic discharge signal ESDS of the first and second PMOS transistor PM
11
and PM
12
and the first and second NMOS transistor NM
11
and NM
12
must be below a reference value, and the electrostatic discharge signal much be enough discharged.
However, as to the conventional art, in the evaluation of the electrostatic discharge characteristics, the P-type bulk terminal is floated without being connected to the ground voltage VSS. Accordingly, in case that the ground voltage VSS terminal is connected to the ground, if a lower electrostatic discharge signal than the minus power supply voltage is applied thereto, the electrostatic discharge signal is discharged only by the N-P-N parasitic bipolar transistor, failing to perform the forward-direction function of the n+/p parasitic diode, which causes a deterioration of the electrostatic discharge characteristics.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an electrostatic discharge protecting circuit in which when an electrostatic discharge signal, a minus voltage at the reference of a ground voltage VSS, is applied, bulk terminals of each NMOS transistor are controlled to be connected to the ground voltage VSS which adds a forward-direction function of an n+/p parasitic diode, to thereby improve an electrostatic discharge characteristics.
To achieve these and other advantages in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided an electrostatic discharge protecting circuit for a semiconductor device including a first block for serving as an output buffer under the control of a first and a second control signals when it is desired to perform a normal operation by being connected to an internal circuit, and serving as an electrostatic discharge protecting circuit by connecting a bulk of a P-type transistor to a power supply unit and a bulk of a N-type transistor to a ground voltage when it is desired to perform an electrostatic discharge characteristics evaluation; a pad for receiving the output from the first block or the electrostatic discharge signal; and a second block for serving as an electrostatic discharge protecti

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