Electrostatic discharge prevention circuits

Details Electrostatic discharge prevention circuits Electrostatic discharge prevention circuits

2011-03-15

2011-03-15

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

07907374

ABSTRACT:
An ESD prevention circuit is provided. The ESD prevention circuit comprises a voltage source, a charge-blocking unit, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and an output unit. The charge-blocking unit is coupled to the voltage source and provides a reverse voltage to control the voltage source to remain at a zero potential when an electrostatic voltage is being generated. The first PMOS transistor is coupled to the charge-blocking unit. The first NMOS transistor is coupled to the first PMOS transistor. The second NMOS transistor is coupled to the first PMOS transistor and the first NMOS transistor. The output unit is coupled to the second NMOS transistor. The electrostatic voltage is affected by the charge-blocking unit and does not raise impendence of the turned-on second NMOS transistor.

REFERENCES:
patent: 5852541 (1998-12-01), Lin et al.
patent: 7027276 (2006-04-01), Chen
patent: 7061737 (2006-06-01), Chen
patent: 2006/0268473 (2006-11-01), Kemper

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