Electrostatic discharge power clamp circuit

Details Electrostatic discharge power clamp circuit Electrostatic discharge power clamp circuit

2001-12-20

2003-04-15

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S575000, C327S324000

Reexamination Certificate

active

06549061

ABSTRACT:

BACKGROUND
TECHNICAL FIELD OF THE PRESENT INVENTION
The present invention generally relates to electrostatic discharge circuits, and more specifically, to electrostatic discharge power clamp circuits.
BACKGROUND OF THE PRESENT INVENTION
Electrostatic Discharge (ESD) events, which can occur both during and after manufacturing of the Integrated Circuit (IC), can cause substantial damage to the IC. ESD events have become particularly troublesome for CMOS and BiCMOS chips because of their low power requirements and extreme sensitivity.
A significant factor contributing to the ESD sensitivity is that the transistors of the circuits are formed from small regions of N-type materials, P-type materials, and thin gate oxides. When a transistor is exposed to an ESD event, the charge applied may cause an extremely high current flow to occur within the device which can, in turn cause permanent damage to the junctions, neighboring gate oxides, interconnects and/or other physical structures.
Because of this potential damage, on chip ESD protection circuits for CMOS and BiCMOS chips are essential. In general, such protection circuits require a high failure threshold, a small layout size and a low Resistive/Capacitive (RC) delay so as to allow high speed applications.
An ESD event within an IC can be caused by a static discharge occurring at one of the power lines or rails. In an effort to guard the circuit against damage from the static discharge, circuits referred to as ESD clamps are used. An effective ESD clamp will maintain the voltage at the power line to a value which is known to be safe for the operating circuits, and not interfere with their operation under normal conditions.
An ESD clamp circuit is typically constructed between a positive power supply (e.g. VDD) and a ground plane, or a ground plane and a negative power supply (VSS). The main purpose of the ESD clamp is to reduce the impedance between the rails VDD and VSS so as to reduce the impedance between the input pad and the VSS rail (i.e. discharge of current between the input to VSS), and to protect the power rails themselves from ESD events.
The never ending demand by the consumer for increased speed in Radio Frequency (RF) devices has resulted in some unique challenges for providing ESD protection in these high speed applications. More specifically, the physical size (e.g. Breakdown voltage) and loading effects of the ESD devices must now be considered in such high speed applications (e.g. 1-200 Giga Hertz range). The capacitive loading of the ESD device itself becomes a major concern for chips running at high frequencies, since the capacitive loading has an adverse effect on performance. For example, the capacitive loading effect of a typical ESD clamp at a frequency of 1 Hz is 0.5 pF, 10 GHz-0.1 pF, and at 100 GHz-0.05pF, 200 Hz-0.01 pF).
In bipolar transistors, there is an inverse relationship between the breakdown voltage and the current gain cutoff frequency known as the Johnson Limit. In each technology generation, the cutoff frequency increases leading to lower collector to emitter breakdown voltages BVCEO. At the same time, mixed voltage applications exist where chips of non-native power supply voltages need to be applied above the BVCEO of the transistor. The term “non-native” as used herein refers to any power supply that is greater than that for which the transistor is constructed.
It would, therefore, be a distinct advantage to have an ESD clamp that could provide substantial benefits in high speed devices while limiting any performance degradation from capacitive loading. It would be further advantageous to have an ESD clamp that provides the ability to raise the clamp and/or trigger condition above the native power supply voltages. The present invention provides such an ESD clamp.
SUMMARY OF THE PRESENT INVENTION
In one aspect, the present invention is an ESD device that is useful in high speed radio frequency applications where size and loading effects are a concern. The ESD device is preferably constructed on a SiGe, SiGeC or equivalent type material that nearly approximates the Johnson Limit curve, and constructed in a Darlington type configuration. In the preferred embodiment of the present invention, the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that of the clamping device, and a frequency cutoff that is higher than that of the clamping device.
In yet another aspect, the present invention is an ESD device preferably constructed on a SiGe, SiGeC or equivalent type material that nearly approximates the Johnson Limit curve, constructed in a Darlington type configuration, and that allows a trigger condition below the BVCEO of the clamp element and above the BVCEO of the trigger element.
In yet a further aspect, the present invention is an ESD device preferably constructed on a SiGe, SiGeC, or equivalent type material that nearly approximates the Johnson Limit curve, constructed in a Darlington type configuration, and where the trigger/clamp rail is level shifted relative to the power supply rail conditions, avoiding the Johnson limit constraint on the trigger and clamp elements.


REFERENCES:
patent: 3535532 (1970-10-01), Merryman
patent: 3629623 (1971-12-01), Sakurai et al.
patent: 3671833 (1972-06-01), Rakes
patent: 4764688 (1988-08-01), Matsumura
patent: 4769560 (1988-09-01), Tani et al.
patent: 5684427 (1997-11-01), Stoddard et al.

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