Electrostatic discharge input protection network

Details Electrostatic discharge input protection network Electrostatic discharge input protection network

1986-12-29

1988-02-09

Carroll, J.

357 41, 357 51, 357 59, 357 65, 357 68, 357 71, H01L 2978, H01L 2702, H01L 2904, H01L 2348

Patent

active

047244712

ABSTRACT:
An improved input network for MOS semiconductor devices intended to increase the device resistance to electrostatic discharge in the input circuit. A series of features comprising round and concentric round contacts and buried contacts, a layer of polycrystalline silicon disposed between the metal input contact and the N+ diffusion layer and enlarged metal contact areas are employed to reduce the tendency toward breakdown by reducing hot spots in the device.

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F. Masuoka et al, "A New Mask ROM Cell Programmed by Through-Hole Using Double Polysilicon Technology", Proceedings of the IEEE International Electron Devices Meeting (1953) pp. 577-579.
J. K. Keller, "Protection of MOS Integrated Circuits from Destruction by Electrostatic Discharge", Proceedings of the 1980 Electrical Overstress/Electrostatic Discharge Symposium, pp. 73-80.

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