Electrostatic discharge immunizing circuit without area penalty

Details Electrostatic discharge immunizing circuit without area penalty Electrostatic discharge immunizing circuit without area penalty

2011-05-31

2011-05-31

Fureman, Jared J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07952844

ABSTRACT:
A chip includes a core circuit, a main electrostatic discharge immunizing circuit, and a secondary electrostatic discharge immunizing circuit. The secondary electrostatic discharge immunizing circuit is disposed beneath a core power ring formed between the core circuit and the main electrostatic discharge immunizing circuit for reaching the aim of protecting the core circuit from damage by electrostatic discharges without area penalty of the chip. Both the main electrostatic discharge immunizing circuit and the secondary electrostatic discharge immunizing circuit include a power clamp and a plurality of current limiters, and keep electrostatic currents from reaching the core circuit with the aid of the power clamp.

REFERENCES:
patent: 4855863 (1989-08-01), Yoshitake
patent: 6114903 (2000-09-01), Bach
patent: 7115952 (2006-10-01), Woo
patent: 2005/0078427 (2005-04-01), Castro

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