Electrostatic discharge (ESD) protection for NMOS pull up transi

Details Electrostatic discharge (ESD) protection for NMOS pull up transi Electrostatic discharge (ESD) protection for NMOS pull up transi

1998-07-13

2000-07-18

Jackson, Stephen W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 361115, 361118, H02H 300

Patent

active

060915951

ABSTRACT:
Electrostatic discharge (ESD) protection is provided for NMOS pull up transistors 700A-H and 702A-H of a 5.0 volt compatible output buffer using 2.5 volt process transistors. The ESD protection includes a p+ guard ring region 901-903 surrounding each pair of NMOS pull up transistors such as 700A, 702A. The p+ guard ring enables pull up of the p- epitaxical region supporting the NMOS pull up transistors during an ESD event. With a first set of series connected NMOS transistors turning on during an ESD event, its surrounding p+ guard ring will pull up the p- epitaxical region around other sets of series connected NMOS transistors to prevent secondary breakdown in the first NMOS pair. Further, ballast resistors 701A-H and 703A-H are included to separate individual pairs of NMOS pull up transistors 700A-H and 702A-H from the pad and from a power supply connection NV3. The ballast resistors enable turn on of additional pairs of NMOS pull up transistors after a first pair turns on during an ESD event to prevent secondary breakdown in the first NMOS pair.

REFERENCES:
patent: 4990802 (1991-02-01), Smooha
patent: 5510728 (1996-04-01), Huang

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