Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2008-05-13
2008-05-13
Sherry, Michael (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S091100, C361S118000
Reexamination Certificate
active
07372681
ABSTRACT:
An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fingered MOS transistor, each finger respectively adapted for coupling between an I/O pad and a first supply line of the IC. An ESD detector is coupled to the I/O pad via a first terminal, and a second terminal is adapted for coupling to a second supply line potential of the IC. A parasitic capacitance is formed between the second supply line potential of the IC and the first supply line potential. A transfer circuit is coupled to a third terminal of the ESD detector and is adapted for biasing at least one gate respectively associated with at least one finger of the multi-fingered MOS transistor.
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Armer John
Jozwiak Phillip Czeslaw
Mergens Markus Paul Josef
Russ Cornelius Christian
Lowenstein & Sandler PC
Patel Dharti H
Sarnoff Corporation
Sarnoff Europe
Sherry Michael
LandOfFree
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