Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device
Reexamination Certificate
1999-04-20
2001-05-22
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
C257S204000, C257S365000, C257S360000, C257S356000, C257S355000
Reexamination Certificate
active
06236073
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge device. More particularly, the present invention relates to an electrostatic discharge device, which can detour the current path and increase the electricity dissipation length.
2. Description of the Related Art
Electrostatic discharge (ESD) is one of the major ways for an integrated circuit (IC) to be damaged in an IC fabrication process. This is especially true for fabrication of a deep sub-micron IC. In order to overcome the problems caused by static electricity, an ESD protective circuit is incorporated onto the input/output (I/O) pads of a complementary metal-oxide-semiconductor (CMOS) IC through an on-chip method.
Since the gate oxide layer becomes thinner as the line width of the semiconductor fabrication process is downsized, the breakdown voltage of the gate oxide layer approaches or is lower than that of the source/drain junction. Hence, the protection provided by the ESD protective circuit becomes less effective. Additionally, design of the inner circuit often follows minimum design rules. Because the inner circuit is not appropriately designed (such as enough spaces for contact-to-diffusion edge and contact-to-gate electrode edge) for resisting the large ESD transient current, the wafer is easily damaged by ESD in highly integrated circuits. Therefore, ESD is one of the major reasons leading to failure in deep sub-micron integrated circuits.
FIG. 1A
is a circuit diagram for a conventional ESD protective circuit. As shown in
FIG. 1A
, in order to protect the internal circuit
10
, the ESD current imported through an input port INP is discharged through an NMOS transistor N
1
to a ground V
SS
.
FIG. 1B
is a schematic circuit diagram of another conventional ESD protective circuit. As shown in
FIG. 1B
, in order to protect the internal circuit
10
, the ESD current can be discharged not only through an NMOS transistor N
1
to the ground V
SS
but also through a PMOS transistor P
1
to a voltage source V
DD
.
FIG. 2
is a schematic, cross-sectional view of the conventional ESD protective circuit shown in FIG.
1
A. As shown in
FIG. 2
, the NMOS transistor N
1
is formed on a substrate
20
. The NMOS transistor N
1
comprises a drain region
22
formed in the substrate
20
, a source region
24
formed in the substrate
20
and a gate electrode
26
formed on the substrate
20
between the source region
24
and the drain region
22
. The gate electrode
26
is isolated from the substrate
20
by a gate oxide layer
25
. A dielectric layer
28
having a drain contact
30
and a source contact
32
formed therein is formed over the substrate
20
, and the drain region
22
is coupled to an input line I/P through the drain contact
30
and the source region
24
is coupled to the ground V
SS
through the source contact
32
.
FIG. 3
is a schematic, top view of the ESD protective circuit in FIG.
2
. The cross-sectional view taken along the line I—I in
FIG. 3
is denoted as FIG.
2
. As shown in
FIG. 3
, circles with declining lines at the midpoint part denote the source contacts
30
and circles with declining lines at both sides denote the drain contacts
32
. The source region
24
and the gate electrode
26
are respectively electrically coupled to the ground V
SS
(as shown in
FIG. 1A
or FIG.
1
B). The source region
22
is electrically coupled to the input line I/P (as shown in
FIG. 1A
or FIG.
1
B). The ESD transient current I
1
flows to the drain region
22
through the drain contact
30
and diffuses in the drain region
22
. Then, the ESD transient current I
1
flows to the ground V
SS
through the source contact
32
.
However, when the gate electrode is nonuniform, some of the channels open relatively early. Moreover, when some of the channels have defects, the ESD transient current I
1
excessively focuses at those channels or at the defects. Therefore, the massive current passes through only a portion of the NMOS transistor N
1
and the temperature of that portion of the NMOS transistor N
1
is high. Hence, the wafer structure is damaged. Additionally, the efficacy of the ESD protective circuit is poor.
SUMMARY OF THE INVENTION
The invention provides an electrostatic discharge protective circuit. By using the invention, the electrostatic discharge transient current path is greatly increased, so that the electricity dissipation length is increased. Hence, the protective efficacy of the electrostatic discharge protective circuit can be improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an electrostatic discharge protective circuit formed on a substrate. A gate electrode is formed over the substrate. A drain region is formed in the substrate at one side of the gate electrode. A source region is formed in the substrate at the other side of the gate electrode. A dielectric layer having a drain contact and a source contact formed therein is formed over the substrate, wherein the drain contact is electrically coupled to the drain region and the source contact is electrically coupled to the source region. A plurality of floating polysilicons is formed on the substrate in the dielectric layer between the drain contact and the gate electrode. Since the floating polysilicons are staggered on the substrate in a checkered pattern, the electrostatic discharge transient current path is greatly increased. Therefore, the electricity dissipation length is greatly increased. Hence, the protective efficacy of the electrostatic discharge protective circuit can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5519242 (1996-05-01), Avery
patent: 5721439 (1998-02-01), Lin
patent: 5838033 (1998-11-01), Smooha
patent: 5917220 (1999-06-01), Waggoner
patent: 6060752 (2000-05-01), Williams
Martine Penilla & Kim LLP
Smith Matthew
United Microelectronics Corp.
Yevsikou V.
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