Electrostatic discharge detection and clamp control circuit

Details Electrostatic discharge detection and clamp control circuit Electrostatic discharge detection and clamp control circuit

1991-08-29

1993-10-19

Deboer, Todd E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361113, H02H 904

Patent

active

052551466

ABSTRACT:
A switching element is connected to an integrated circuit for shunting an ESD pulse away from the integrated circuit features. A plurality of detection circuits responsive to typical ESD waveform characteristics provide logical control of the switching means. In the preferred embodiment, a NAND gate drives the switching element. The first input to the NAND gate is a first RC network having a first time constant that exceeds the characteristic rise time of the typical ESD pulse, but not the characteristic duration of the typical ESD pulse. The second input to the NAND gate is a feedback loop from the NAND gate output. The feedback loop includes a second RC network having a second time constant that exceeds the duration of a noise pulse, a third RC network having a third time constant that approximates the characteristic duration of the typical ESD pulse, and an inverter between the second and third RC networks. Application of the ESD pulse causes the first input to drive the NAND gate, thus turning on the switching element, and if the ESD pulse is still present when the second time constant is exceeded, the switching means is latched on via the second input until the third time constant is exceeded.

REFERENCES:
patent: 4363068 (1982-12-01), Burns
patent: 4692834 (1987-09-01), Iwahashi et al.
patent: 4787007 (1988-11-01), Matsumura et al.
patent: 4890187 (1989-12-01), Tailliet et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980 "Voltage Programmable Protect Circuit" Hoffman et al.

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