Electrostatic discharge compatible voltage reference buffer

Details Electrostatic discharge compatible voltage reference buffer Electrostatic discharge compatible voltage reference buffer

2000-11-22

2003-11-25

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C327S310000

Reexamination Certificate

active

06654214

ABSTRACT:

FIELD
Embodiments according to the present invention relate to integrated circuits, and more particularly, to electrostatic discharge protection of discrete time switched capacitor analog circuits.
BACKGROUND
For many discrete time (or sampled-data) analog circuits, such as for example an ADC (Analog-to-Digital Converter), it is desirable to provide one or more voltage reference buffers with low impedance. For many applications, voltage reference buffers are bypassed with external capacitors. A relatively large external capacitor may help a voltage reference buffer provide a constant reference voltage due to the charge reservoir stored in the external capacitor. As a result, a bypassed voltage reference buffer is connected to an external pin on an IC (Integrated Circuit) so that the external capacitor may be connected to the voltage reference buffer.
This is illustrated in
FIG. 1
, where voltage reference buffer
102
is bypassed by external capacitor
104
, and voltage reference buffer
106
is bypassed by external capacitor
108
. Capacitors
104
and
108
are connected to pads
110
and
112
, respectively, via bond wires
114
and
116
, respectively. In
FIG. 1
, differential signal notation is employed, where a differential signal x means that the actual voltage is x above a common-mode voltage. For example, voltage reference buffer
102
provides a differential voltage V
ref
and voltage reference buffer
106
provides a differential voltage −V
ref
, but the actual reference voltage provided by reference buffer
102
is a voltage V
ref
above a common-mode voltage and the actual reference voltage provided by reference buffer
106
is a voltage V
ref
below the common-mode voltage. Furthermore, in practice both differential voltages V
ref
and −V
ref
may be realized at the output port of a differential amplifier (not shown), but for simplicity two separate reference buffer circuits are indicated in FIG.
1
.
Because voltage reference buffers
102
and
106
drive external pins on IC
118
, there should be compatibility with ESD (Electrostatic Discharge) protection. Usually, ESD protection is comprised of primary and secondary ESD protection. Primary ESD protection often involves the use of CMOS (Complementary Metal Oxide Semiconductor) devices having relatively very large dimensions, and located close to the pad (or pads) that will in turn be connected to an external pin (or pins). Secondary ESD protection often involves the use of CMOS devices with much smaller dimensions than those used for primary ESD protection.
ESD current is limited between the primary and secondary ESD sections of an IC by using one or more resistors. For many CMOS technologies, these resistors may be on the order of 75&OHgr;. Because secondary ESD protection involves relatively small devices, it is often used for complex core circuits such as ADCs or DACs (Digital-to-Analog Converter). This is illustrated in
FIG. 1
, where dashed lines
102
indicate boundaries between sections involving primary and secondary ESD protection. Resistors
122
limit current between the primary and secondary ESD sections.
Although the use of secondary ESD protection is usually practical for ADCs and DACs, the series ESD 75&OHgr; resistors used to limit current between the primary and secondary ESD sections may lead to voltage reference buffer circuits with too large of an impedance. In particular, for switched capacitor circuits, the combination of capacitors and the 75&OHgr; ESD resistors may lead to a RC time constant that is too large. This is illustrated in
FIG. 1
, where capacitors
124
are switched so as to be connected to voltage reference buffer circuit
102
and capacitors
126
are switched so as to be connected to voltage reference buffer circuit
106
. If these capacitors are switched so as to be connected in parallel to one another, then the effective capacitance in series with the ESD resistors may lead to unacceptably high RC time constants. This may not be compatible with high switching speeds because the individual capacitors do not have time to be charged or discharged sufficiently close to their asymptotic values.


REFERENCES:
patent: 5552748 (1996-09-01), O'Shaughnessy
patent: 5850195 (1998-12-01), Berlien et al.

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