Electrostatic discharge circuit for high speed, high voltage cir

Details Electrostatic discharge circuit for high speed, high voltage cir Electrostatic discharge circuit for high speed, high voltage cir

1994-01-13

1995-12-05

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 91, H02H 322

Patent

active

054735009

ABSTRACT:
A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node. The first controlled path is from the signal node to V.sub.cc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V.sub.cc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a gate tied at V.sub.cc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V.sub.cc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor, if low voltage circuitry is tied to the signal node. The fourth transistor includes a gate that is tied high by connection of the gate to ground via a transistor and inverter.

REFERENCES:
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