Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2005-05-31
2005-05-31
Leja, Ronald (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06900970
ABSTRACT:
An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad31to a first power supply node (76).
REFERENCES:
patent: 4734752 (1988-03-01), Liu
patent: 4870530 (1989-09-01), Hurst
patent: 4930037 (1990-05-01), Woo
patent: 4987465 (1991-01-01), Longcor
patent: 5208719 (1993-05-01), Wei
patent: 5345357 (1994-09-01), Pianka
patent: 5361185 (1994-11-01), Yu
patent: 5477414 (1995-12-01), Li et al.
patent: 6075271 (2000-06-01), Smith
patent: 6091594 (2000-07-01), Williamson et al.
patent: 6284616 (2001-09-01), Smith
patent: 6327126 (2001-12-01), Miller
patent: 6329692 (2001-12-01), Smith
patent: 6373104 (2002-04-01), Smith
patent: 6624998 (2003-09-01), May et al.
patent: 0385581 (1990-09-01), None
patent: WO/01/47018 (2001-06-01), None
Duvvury et al., “Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection,” IEEE, 1992 International Reliability Physics Symposium (IRPS), pp. 141-150, no month.
Nikolaidis et al, “Impact of I/O Buffer Configuration on the ESD Performance of a 0.5um CMOS Process,” 1995 EOS/ESD Symposium 95-34, pp. 1.5.1-1.5.9, no month.
Krakauer et al, “ESD Protection in a 3.3V Sub-Micron Silicided CMOS Technology,” EOS/ESD 1992 Symposium 92-250, pp. 5B.4.1-5B.4.8, no month.
Guggenmos et al., “A New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stress,” EOS/ESD Symposium Proceedings 1991, pp. 74-76, no month.
Smith, “An Anti-Snapback Circuit Technique for Inhibiting Parasitic Bipolar Conduction During EOS/ESD Events,” EOS/ESD Symposium 99-62, pp. 2A.1.1-2A.1.8, no month 1999.
Chen, “The Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors,” IEEE Transactions on Electron Devices, vol. 35, No. 12, Dec., 1988, pp. 2140-2150.
Chen, “Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors,” 1988 EOS/ESD Symposium Proceedings, pp. 212-219, no month.
Polgreen et al., “Improving the ESD Failure Threshold of Silicided nMOS Output Transistors by Ensuring Uniform Current Flow,” 1989 EOS/ESD Symposium Proceedings, pp. 167-174, no month.
Dabral et al, Core Clamps for Low Voltage Technologies, INTEL Corporation, Santa Clara, CA, pp. 3.6.1-3.6.9, no date.
Khazhinsky Michael G.
Miller James W.
Stockinger Michael
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Susan C.
Leja Ronald
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