Electrostatic discharge circuit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000

Reexamination Certificate

active

08035937

ABSTRACT:
An electrostatic discharge device has relatively superior characteristics for protecting a gate insulation layer of an input buffer transistor of a semiconductor device from static electricity while minimizing signal delay. The electrostatic discharge circuit includes a main electrostatic discharge section configured to discharge static electricity inputted to an input/output pad to at least one voltage line, an input impedance section configured to adjust an amount of current flowing from the input/output pad depending upon a frequency of an input signal of the input/output pad, an auxiliary electrostatic discharge section connected to the input impedance section and configured to discharge the static electricity inputted to the input/output pad to the at least one voltage line, and an input buffer connected between the auxiliary electrostatic discharge section and an internal circuit.

REFERENCES:
patent: 6433985 (2002-08-01), Voldman et al.
patent: 7218491 (2007-05-01), Jaussi et al.
patent: 7459754 (2008-12-01), Kang
patent: 2006/0126236 (2006-06-01), Vice
patent: 2008/0179681 (2008-07-01), Kwak
patent: 2008/0259511 (2008-10-01), Worley
patent: 2009/0021872 (2009-01-01), Ker et al.
patent: 2007-234718 (2007-09-01), None
patent: 2008-532308 (2008-08-01), None
patent: 2008-547223 (2008-12-01), None
patent: WO 2006/092756 (2006-09-01), None
patent: WO 2007/001860 (2007-01-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Apr. 21, 2010.

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