Electrostatic damage protection circuit and dynamic random...

Details Electrostatic damage protection circuit and dynamic random... Electrostatic damage protection circuit and dynamic random...

1998-12-18

2001-05-29

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06239958

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic damage protection circuit (hereinafter referred to simply as a protection circuit) provided in a semiconductor integrated device to prevent electrostatic damage, and also to a dynamic random access memory (hereinafter referred to as a DRAM).
2. Description of the Related Art
In the recent semiconductor integrated device technology, CMOS ICs (Complementary Metal Oxide semiconductor Integrated Circuits) are most widely used because of their advantage of being capable of operating with low power and achieving a high integration density. MOS transistors used in CMOS ICs have a structure consisting of a thin gate oxide film formed on a semiconductor substrate, a gate electrode formed on the gate oxide film, and source and drain electrodes wherein the gate electrode and source and drain electrodes are isolated from one another by the gate oxide film. The disadvantage arising from such a structure and thus essential to the CMOS IC is that the gate oxide film is easily damaged by an external electrostatic surge. To ease this problem, all terminals, no matter whether they are input terminals or output terminals, are protected by protection circuits.
FIG. 2
illustrates a conventional protection circuit for protecting input terminals, and
FIG. 3
illustrates a conventional protection circuit for protecting output terminals.
The input terminal protection circuit includes a p-channel MOS transistor (hereinafter referred to as a PMOS transistor)
1
whose gate and source are connected to a power supply line Lv for supplying a voltage VDD so that the PMOS transistor
1
is fixed to an off-state, and an n-channel MOS transistor (hereinafter referred to as an NMOS transistor)
2
whose gate and source are connected to a ground line Lg for supplying a ground voltage GND so that the NMOS transistor
2
is also fixed to an off-state. An input pad Pi serving as an input terminal is connected to the drains of the PMOS transistor
1
and the NMOS transistor
2
. The input pad Pi connected to the drains of the PMOS transistor
1
and the NMOS transistor
2
is also connected via a gate protection resistor
3
to the gates of transistors
4
a
and
4
b
of an internal circuit
4
to be protected.
In this input terminal protection circuit of the widely used type, if an electrostatic surge is input to the input pad Pi, the resistor
3
produces a delay in the surge voltage applied to the gates of the internal circuit
4
to be protected, and the PMOS transistor
1
and the NMOS transistor
2
absorb the electrostatic surge into the power supply line Lv and the ground line Lg.
On the other hand, the output terminal protection circuit includes a PMOS transistor
5
whose gate and source are connected to a power supply line Lv for supplying a voltage VDD so that the PMOS transistor
5
is fixed to an off-state, and an NMOS transistor
6
whose gate and source are connected to a ground line Lg for supplying a ground voltage GND so that the NMOS transistor
6
is also fixed to an off-state. An output pad Po serving as an output terminal is connected to the drains of the PMOS transistor
5
and the NMOS transistor
6
. The output node N of an internal circuit
7
to be protected is connected to an output transistor
7
a
which turns on and off between the node N and the power supply voltage VDD and also to an output transistor
7
b
which turns on and off between the node N and the ground voltage GND, wherein the output node N is also connected the drains of the PMOS transistor
5
and the NMOS transistor
6
.
In the output terminal protection circuit of this type, an electrostatic surge entering the circuit via the output pad Po toward the node N is shunted by the PMOS transistor
5
and the NMOS transistor
6
thereby enhancing the resistance of the internal circuit
7
against the electrostatic damage.
With the advancement in the microfabrication technology, it is becoming possible to produce smaller-sized element devices. However, it is becoming more difficult to effectively protect CMOS ICs including such small sized devices from electrostatic damage by conventional protection circuits. The operation of the conventional protection circuit is described below, and problems in the conventional protection circuit are discussed.
If an electrostatic surge enters the circuit via the input pad Pi, a breakdown occurs between the substrate and the drain of the PMOS transistor
1
or the NMOS transistor
2
, and a parasitic PNP or NPN transistor associated with the PMOS transistor
1
or the NMOS transistor
2
turns on. As a result, the surge current is absorbed as a bipolar current into the power supply line Lv or the ground line Lg. This means that only when the drain voltage reaches a breakdown voltage, the PMOS transistor
1
and the NMOS transistor
2
can provide their protective function. In most transistors except for special transistors designed for dedicated use as protective transistors and high-voltage transistors, the impurity diffused into the drain and source regions slightly penetrates into a region under the gate. As a result, an end portion of the gate overlaps the drain impurity diffusion layer via the gate oxide film. Therefore, in the conventional protection circuit, the part of the gate oxide film sandwiched between the drain impurity diffusion layer and the gate is subjected to the stress of a voltage equal to the breakdown voltage until the breakdown occurs.
To prevent the end portion of the gate oxide film of such a transistor structure from being damaged, it is required that a breakdown should occur at the drain before the gate oxide film is damaged. In other words, it is required that the thickness of the gate oxide film should be selected to be thick enough that the intrinsic breakdown voltage of the gate oxide film becomes higher than the breakdown voltage of the drain. The input terminal protection circuit is provided to protect the gates of transistors of the internal circuit
4
. To this end, the input terminal protection circuit is constructed with the PMOS transistor
1
, the NMOS transistor
2
, and the resistor
3
so that a surge voltage is delayed by the resistor
3
thereby allowing the surge voltage to be shunted into the power supply line Lv and the ground line Lg.
When the thickness of the gate oxide film is reduced, the resistance of the resistor
3
should be increased to a sufficiently high value to protect the thin oxide film. However, the increase in the resistance also causes the gate signal to be delayed during the normal operation, and thus the requirement of high-speed operation cannot be met. Also in the output terminal protection circuit, the damage of the gate oxide film at an end of the gate of the MOS transistor
7
a
or
7
b
of the internal circuit
7
or the PMOS protection transistor
5
or the NMOS protection transistor
6
is a serious problem.
The gate oxide film becomes thinner with the reduction in the size of transistors. This results in a reduction in the difference between the intrinsic breakdown voltage of the gate oxide film and the breakdown voltage of the drain. That is, in recent semiconductor integrated devices, because of the very small difference between the breakdown voltage of the drain and the intrinsic breakdown voltage of the gate oxide film, the gate oxide film is often damaged when a voltage close to the intrinsic breakdown voltage is applied across the gate oxide film. Even when the gate oxide film is not damaged, such a surge current can cause carriers to be injected into the gate oxide film, thus causing degradation in the characteristics of the PMOS transistor
1
or the NMOS transistor
2
. As described above, in the conventional technique in which the PMOS transistor
1
and the NMOS transistor
2
are forced into breakdown and then bipolar currents are absorbed into the power supply line Lv and the ground line Lg, it is required that the drain breakdown voltage should be lower than the intrinsic breakdown voltage of the

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