Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-24
2003-09-16
Hassanzadeh, P. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S716000, C438S714000, C427S569000, C118S728000, C118S720000, C156S345510, C156S345300
Reexamination Certificate
active
06620736
ABSTRACT:
This invention relates to the semiconductor wafer plasma processing, particularly to plasma deposition and etching processes, in which regions at the edge of the wafer are susceptible to contamination by ionized material from the processing space.
BACKGROUND OF THE INVENTION
In the deposition of material layers onto semiconductor wafers, it is necessary to control coverage of the edge region of the wafer, particularly on the so-called “bevel” where the wafer is no longer flat. This has become increasingly important with the introduction of the use of copper as an interconnect material. Copper, as a contaminant in silicon, prevents the functioning of devices such as transistors that are produced on the wafer. Areas of a semiconductor wafer inward of the beveled edge of the wafer are coated during processing with an oxide layer or a barrier material before copper is applied. The edge of the wafer, however, is either not coated with the oxide or barrier material or such coating is not well controlled. As a result, the coating of such areas in the region of the wafer edge must be carefully avoided if contamination of the silicon and resulting damage to devices being made on the wafer is to be prevented. These areas on which copper deposition is to be avoided include the edge around the front side of the wafer as well as the wafer perimeter and the entire backside surface of the wafer. These areas are also areas at which the wafer is subject to handling. Therefore, with copper and other deposited materials, it is preferred that deposited material thickness around the bevel tapers to zero in a controlled way.
One method of controlling edge deposition has been through the use of shadow masks, that is, masks that do not contact the wafer, to shield the edge of the wafer from deposition. Another method has been through the use of clamps or clamping rings, which do contact the wafer, to shield the edge from deposition. Each of these methods has disadvantages. For example, deposition on the mask or clamp leads to particle problems from loosely adhered material. Also, as a significant amount of material is deposited on the shadow ring or clamp, the size of the clamp changes, which affects the size of the region which the clamp or mask shields.
Currently used deposition systems often include wafer supports such as electrostatic chucks that do not overlap the wafer bevel. In the cases of these non-overlapping supports, bevel area deposition is more difficult to control.
Further, in a high density plasma etching apparatus, the etch rate at the bevel must be controlled to prevent over etching. In this case, it is desirable to steer ions that are causing the etching away from the bevel, thereby reducing the etch rate there. In some cases, it may be desirable to increase etch rate locally by steering the ions toward the bevel.
Accordingly, the need exists for the control of ions at the edge region of a wafer during ionized deposition and etching.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to control the deposition of coating material at the edge region of a semiconductor wafer, particularly in cases where a large fraction of the incident material is ionized, such as in Ionized Physical Vapor Deposition systems (iPVD).
The present invention is based in part on the principle that ions approaching the edge regions of a semiconductor are subjected to electrostatic deflection in the presence of an electric field. In accordance with principles of the present invention, the electric field at the edge region of the wafer is tailored so as to control deposition at the edge bevel of the wafer.
The invention is particularly useful where ionized material emerges from a plasma and is deposited upon a semiconductor wafer. In cases where the wafer is biased so as to acquire a non-zero potential with respect to the bulk of the plasma, the potential accelerates the ions in a direction more aligned with the direction of the sheath field that forms between the plasma and the biased wafer.
In accordance with certain principles of the invention, the sheath field is adjusted to deflect ions away from the wafer bevel towards a region where they can be captured.
According to certain embodiments of the invention, a ring is provided outside the wafer and is biased with respect to the plasma to shape the field around the wafer edge. As a result, ions arriving at the sheath are deflected by the sheath field and then pass through a field-free region, thereafter intercepting the shield instead of the wafer bevel.
In one embodiment of the invention, a metallic ring is provided that is in contact with the surface of an electrostatic chuck on which the wafer is held. The chuck is biased and a similar bias appears on the ring. A protrusion is provided on the ring to enhance the field locally, which leads to a local curvature of the sheath surface, so that an ion that would have intercepted the wafer bevel will instead be deflected. The ring has a profile that controls the probability that the ion will be collected by the shield rather than arriving at the wafer. The details of this profile may be based on gas pressure and the sticking coefficient of the ion on the ring and on the chuck as a function of ion energy, charge state, and incident angle, and as a function of the desired deposition profile on the wafer bevel.
In another embodiment of the invention, a ring is provided that is grounded while the chuck is biased, or that is biased to a different level than is the wafer. The ring may, for example, be biased to a level such that the average potential difference between the bulk of the plasma and the ring has a lower magnitude than the average difference between the wafer DC bias potential and the bulk plasma potential. In this case, a sheath will still exist over the ring although its thickness may be reduced. In this case, no field free region, as mentioned above, will exist. Material may, however, tend to be attracted towards the wafer and chuck, which would be preferred where such coating is desirable. Alternatively, the ring may be biased separately from the wafer so that the average difference between the potential of the ring and that of the bulk plasma is higher than the average difference between the potential of the wafer and that of the bulk plasma. This allows ions to be scavenged from the edge region of the wafer, and ions penetrating between the shield and the wafer to be attracted towards the shield, with the result of reducing deposition on the bevel.
The principles employed in the above described embodiments may also be applied to control the rate of etching at the edge region of a wafer. Etching is generally greatest where there is the largest arrival rate of ionized material. A reduction of the bevel etch rate can be achieved by providing deflection of ions away from the edge of the wafer.
Multiple rings may be combined that are not in mutual electrical contact. Such rings may be maintained at different potentials and have different other properties. For example, an outer shield may be grounded and textured to improve adhesion of deposited material. Where wafer bias is relatively large, resputtering of deposited material from the wafer occurs, but a grounded outer shield limits or eliminates resputtering from the outer shield. Alternatively, the outer shield may be separately biased to affect the plasma parameters in desirable ways, or it may be formed of a different material such as a dielectric material.
Electrical continuity from the chuck to the ring can be achieved by a direct DC connection, or by capacitance between the chuck body and the ring.
In the case of deposition, the ring is preferably designed so that, as material collects upon it, its profile performs within specification from immediately after installation up to the time it is removed for cleaning or replacement.
These and other objectives and advantages of the present invention will be more readily apparent from the following detailed description.
REFERENCES:
patent: 4962727 (1990-10-01), Harada
patent: 55
Hassanzadeh P.
Tokyo Electron Limited
Wood Herron & Evans L.L.P.
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