Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2002-11-29
2004-03-23
Tan, Vibol (Department: 2819)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S091200, C361S111000, C361S118000, C257S355000, C257S357000, C326S047000, C326S101000
Reexamination Certificate
active
06710991
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic-breakdown-preventive and protective circuit for a semiconductor-device provided with power-source lines and ground lines dedicated to a plurality of internal logic circuits.
2. Description of the Related Art
In recent years, a semiconductor integrated-circuit device (may be hereafter referred to as a semiconductor device or a device) uses an internal circuit by driving it with a dedicated power source line and ground line for each functional block. Because an operating voltage is lowered, a noise-malfunction margin tends to decrease. For example, when a specific circuit block switches to a state of consuming much power, a drop of a power-source voltage due to the above state propagates to power-source lines of another circuit block to prevent a circuit block to be easily influenced by the voltage drop from malfunctioning. This type of the device has a problem that it easily causes an electrostatic breakdown. This is described below by using an example of providing independent power-source line and ground line dedicated to an internal circuit for two circuit blocks.
FIG. 12
shows a layout image diagram on the device chip of a conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit.
FIG. 13
shows a circuit diagram of the conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit. As shown in
FIGS. 12 and 13
, a conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit uses a semiconductor device
100
in which a circuit block A
101
(internal-circuit region A) and a circuit block B
102
(internal-circuit region B) have an equal supply potential but they have power-source systems independent from each other and the power-source system of an input/output circuit
103
(input/output circuit region) is independent, and an inverter
20
connected to a circuit block A is constituted so as to receive an output of an inverter
30
connected to the circuit block B
102
as an input signal through a signal line (wiring resistor)
25
.
In a circuit having the configuration of a pair of output and input for interfacing the above two circuit blocks each other, when an electrostatic surge is applied between a power-source line
21
for the circuit block A
101
(region A) and a ground line
32
for the circuit block B
102
(region B), the gate (oxide film) of a P-channel MOS (Metal-Oxide Semiconductor which is hereafter referred to as PMOS) transistor
23
constituting the inverter
20
is easily broken down. Because there is not a route for an electrostatic surge to pass from the power-source line
21
for the circuit block A
101
to the ground line
32
for the circuit block B
102
, the electrostatic surge flows through gates of the N-channel MOS (Metal-Oxide Semiconductor which is hereafter referred to as NMOS)
34
of the inverter
30
and the PMOS transistor
23
of the inverter
20
. Even if an electrostatic surge is applied between the power-source line
31
for the circuit block B
102
and the ground line
22
for the circuit block A
101
or between the power-source line
21
for the circuit block A
101
and the power-source line
31
for the circuit block B
102
, the PMOS transistor
23
constituting the inverter
20
or the gate (oxide film) of the NMOS transistor
24
is broken down because there is not a route through which the electrostatic surge passes. To settle this type of problem, an improved protective circuit is used.
FIG. 14
shows a layout image diagram on the device chip of a conventional improved semiconductor-device electrostatic-breakdown-preventive and protective circuit.
FIG. 15
shows a circuit diagram of a conventional improved semiconductor-device electrostatic-breakdown-preventive and protective circuit. In the conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit, by setting a protective transistor
10
between a power-source line
11
and a ground line
12
for an input/output circuit
103
set to the circumferential portion of a device chip, setting protective transistors
26
and
28
between the power-source line
11
and ground line
12
for the input/output circuit
103
and a position between the power-source line
21
and ground line
22
for the circuit block A
101
respectively, and moreover setting protective transistors
27
and
29
between the power-source line
11
and ground line
12
for the input/output circuit
103
and a position between the power-source line
31
and the ground line
32
for the circuit block B
102
respectively, a route for a surge to pass through the protective transistors
28
,
10
, and
27
is secured even if the surge is applied between the power-source line
21
of the circuit block A
101
and the ground line
32
for the circuit block B
102
and moreover, a delay is provided so that a gate oxide film of the PMOS transistor
23
is not broken down before the surge completely flows through these three protective transistors and a surge voltage is not applied to a gate film from the signal line (protective resistor)
25
. Thus, constituting a protective circuit by passing through two or three protective transistors is superior in that the transistors can be easily arranged.
As shown by the layout image diagram of the device chip in
FIG. 14
, because the power-source lines (terminals)
21
and
31
and ground lines (terminals)
22
and
32
for internal blocks intersects the power-source line (terminal)
11
and ground line (terminal)
12
for the input/output circuit at the circumferential portion of the chip with a vertical-height difference, it is possible to easily arrange protective transistors in the vicinity of the intersection. By arranging protective transistors on the intersecting portion, it is possible to easily constitute the protective-circuit network shown in FIG.
15
and protect the gate oxide film of a circuit for interfacing internal circuits each other from an electrostatic surge.
However, because the clock frequency of a device rises, the so-called salicide structure for minimizing the parasitic resistance of a transistor is introduced, an input/output-circuit region is divided into a plurality of subregions, and the total number of protective transistors (number of protective transistors passing from start to end points of an electrostatic surge) constituting a protective-circuit network increases. Therefore, the number of cases is increased in which it is impossible to prevent a gate (oxide film) from being broken down by only increasing the resistance value of the signal line (protective resistor)
25
.
SUMMARY OF THE INVENTION
The present invention provides a compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device performing high-speed operations and capable of solving various problems to which the above-described improved protective-circuit network has become unable to respond, such as the problem of lowered the response characteristic of the protective-circuit network due to changes in process configuration and increases in the number of divided input/output-circuit regions, without increasing an area of the protective circuit or changing processes.
A first aspect of the invention provides an electrostatic-breakdown-preventive and protective circuit for a semiconductor-device, the circuit comprising: a first power-source line and a first ground line for supplying bias to a first internal block; a second power-source line and a second ground line for supplying bias to a second internal block; a third power-source line and a third ground line for supplying bias to an input/output circuit portion; at least one of a first protective transistor provided between the first power-source line and the second power-source line and a second protective transistor provided between the first ground line and the second ground line; third protective transistors respectively disposed at at least two of a position between the fir
Oki Electric Industry Co. Ltd.
Tan Vibol
Volentine & Francos, PLLC
LandOfFree
Electrostatic-breakdown-preventive and protective circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrostatic-breakdown-preventive and protective circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic-breakdown-preventive and protective circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3270234