Electrostatic breakdown prevention circuit for semiconductor...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000

Reexamination Certificate

active

06847512

ABSTRACT:
A high impedance can be maintained at a back gate of a MOS transistor constituting a CMOS integrated circuit when power is not supplied, and is switched to an impedance lower than the impedance in use of the CMOS integrated circuit by a switch driven by a power supply of the CMOS integrated circuit. Thus, it is possible to prevent surge breakdown and electrostatic breakdown, and to prevent occurrence of latch up breakdown.

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patent: 6529536 (2003-03-01), Taguchi
patent: 6583475 (2003-06-01), Makita et al.

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