Electrostatc discharge protection network

Details Electrostatc discharge protection network Electrostatc discharge protection network

1996-06-10

1998-02-24

Young, Brian K.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 257355, H02H 322

Patent

active

057216568

ABSTRACT:
An electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.

REFERENCES:
patent: 5086365 (1992-02-01), Lien
patent: 5208719 (1993-05-01), Wei
patent: 5515226 (1996-05-01), Tailliet
patent: 5521783 (1996-05-01), Wolfe et al.
patent: 5541801 (1996-07-01), Lee et al.
patent: 5631793 (1997-05-01), Ker et al.
K. Narita et al., A Novel On-Chip Electrostatic Discharge (ESD) Protection For Beyound 500MHz DRAM; IEDM Proceeding, 1995; pp. 539-542.

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