Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2001-02-28
2004-09-21
King, Roy (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S103000, C205S104000, C205S118000, C205S123000, C205S149000, C205S157000, C205S186000, C205S187000, C205S219000
Reexamination Certificate
active
06793796
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to electroplating methods and, in particular, to processes for electrodeposition of metal into small integrated circuit features such as vias and trenches that avoid formation of defects.
BACKGROUND
To achieve faster operating speeds, integrated circuits (IC's) are being developed with smaller feature sizes and higher densities of components. Conductivity of metal interconnections has emerged as a limitation in the development of these high performance devices. Thus, future generations of IC's will tend to substitute copper for the presently used aluminum conductors.
Forming electrically conducting vias, contacts, and conductors of copper or other metals becomes increasingly challenging as feature sizes are reduced. Techniques for forming such metal features include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and electrochemical deposition (also referred to as electroplating or electrodeposition.)
The general nature of the electroplating process is well known. The wafer is immersed in an electrolytic bath containing metal ions and is biased as the cathode in an electric circuit. With the solution biased positively, the metal ions become current carriers which flow towards and are deposited on the exposed surfaces of the wafer. Electroplating is particularly well suited for the formation of small embedded damascene metal features due to the ability to readily control the growth of the electroplated film for bottom-up filling without voids, and due to the superior electrical conductivity characteristics of the electroplated film. However, there are also several obstacles which need to be overcome to fully realize these advantages.
One challenge facing damascene processing techniques is the difficulty of initiating the growth of the metal film within recessed features without forming voids or seams. In typical PVD and some CVD processes, metal may preferentially deposit near the top of recessed features leading to a “bottleneck” shape. Further plating of metal onto the bottleneck may result in sealing the top of the feature before completely filling the feature with metal, creating a void. Voids increase the resistance of the conductor over its designed value due to the absence of planned-for conductor. Also, trapped electrolyte in sealed voids may corrode the metal. This may lead to degraded device performance or device failure in extreme cases.
Other problems include providing even thickness of an electroplated layer across a die on a semiconductor wafer and avoiding defects in the electroplated metal that are subject to attack during a subsequent chemical mechanical polishing step as part of the IC fabrication process. What is needed is an electroplating technique that produces metal films and features without voids or defects.
SUMMARY
Use of an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, provides an electroplating method that avoids defects in plated films while providing good filling and thickness distribution.
Four distinct phases of electrofilling a patterned substrate having a field region and a plurality of recessed features of varying aspect ratios have been identified. In the first phase, the patterned substrate onto which a seed layer has been deposited, is immersed in an electroplating bath. The second phase involves nucleation and island bridging of the seed layer to form a thin conformal conducting film everywhere on the surface. In the third phase, metal is preferentially deposited on the bottom of the features having the highest aspect ratios and proceeds to features having lower aspect ratios as the current density is raised. Finally, the fourth phase pertains to the filling of low aspect ratio features in a rapid, substantially conformal manner.
A method of electroplating a metal onto a surface having a metal seed layer, where the surface comprises a field region and recessed features with a range of aspect ratios, starts with contacting the surface with an electroplating solution comprising metal ions, a suppressor additive, an accelerator additive, and a leveler additive under conditions where the metal seed layer is cathodically polarized with respect to the electroplating solution prior to or less than approximately 5 seconds following contacting. In the second phase, a DC cathodic current density is applied through the surface at a first value of current density that is sufficiently small that depletion of metal ions and the additives is absent at both the field region and the recessed features, to create a substantially conformal thin conductive metal film on the surface. In the third phase, a DC cathodic current density having a second value is applied through the surface, where the second value is selected so that electroplating occurs preferentially on bottoms of recessed features having the largest aspect ratios. As the current density is increased, electroplating progresses to features having smaller aspect ratios. During the second phase, the applied current density is increased from the second value until all recessed features are filled to where they have aspect ratios less than about 0.5. Finally, the current density is increased to a third value that provides a condition of conformal plating, filling recessed features and plating metal onto the field region.
A method is also provided for electroplating a metal onto a continuous conducting surface having a field region and recessed features with a range of aspect ratios. Using an electroplating bath including metal ions, a suppressor additive, an accelerator additive, and a leveler additive, a DC cathodic current density is applied through the surface, where the current density value is selected so that electroplating occurs preferentially on bottoms of recessed features having the largest aspect ratios. The current density is increased until all recessed features have aspect ratios less than 0.5. Finally, the current density is increased to a final value that provides a condition of conformal plating, filling recessed features and plating metal onto the field region.
Including a leveling additive in the electroplating bath modifies grain growth during the third phase and produces a film that is less susceptible to attack during chemical mechanical processing (CMP). Absent inclusion of levelers in the plating bath, the growth of the film in the middle of the features tends to be faster than the growth on the sidewalls. The addition of levelers slows down the growth rate in the center of the features, particularly as the deposit approaches the tops of the openings. Although the benefits of using levelers in the plating bath are not readily apparent immediately after plating, copper films produced without levelers tend to have more holes in the deposit after copper is removed in the field region. Including a leveling additive also reduces the overall topography of the final deposit reducing the total time needed for CMP processing. The thickness of the deposited film is more uniform across the wafer when levelers are included in the electroplating bath and a finer grain structure is obtained.
REFERENCES:
patent: 2733198 (1956-01-01), Nobel et al.
patent: 2842488 (1958-07-01), Strauss et al.
patent: 2882209 (1959-04-01), Brown et al.
patent: 2972572 (1961-02-01), Cope, Jr. et al.
patent: 3956120 (1976-05-01), Kardos et al.
patent: 4092226 (1978-05-01), Laing et al.
patent: 4272335 (1981-06-01), Combs
patent: 4461680 (1984-07-01), Lashmore
patent: 4555315 (1985-11-01), Barbieri et al.
patent: 4563399 (1986-01-01), Wright, Jr.
patent: 5232575 (1993-08-01), Dodd
patent: 5252196 (1993-10-01), Sonnenberg et al.
patent: 5618634 (1997-04-01), Hosoda et al.
patent: 5935762 (1999-08-01), Dai et al.
patent: 5936707 (1999-08-01), Nguyen et al.
patent: 5939788 (1999-08-01), McTeer
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6074544
Henri Jon
Mayer Steven T.
Reid Jonathan D.
Smith David
Varadarajan Sesha
Beyer Weaver & Thomas LLP.
Leader William T.
LandOfFree
Electroplating process for avoiding defects in metal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electroplating process for avoiding defects in metal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electroplating process for avoiding defects in metal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3258938