Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Involving measuring – analyzing – or testing
Reexamination Certificate
2002-01-11
2004-09-21
King, Roy (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Involving measuring, analyzing, or testing
C204S228100, C205S106000
Reexamination Certificate
active
06793792
ABSTRACT:
BACKGROUND
The present application relates to the field of metal deposition and more particularly to methods and systems for electroplating metal.
Metal layers can be formed by electroplating metal on a conductive surface. For example, solder bumps for microelectronic devices can be electroplated on contact pads, and the electroplated solder bumps can be used to provide electrical and/or mechanical interconnection to a next level of packaging such as another microelectronic device and/or a printed circuit board. More particularly, a continuous underbump metallurgy layer can be provided on a microelectronic substrate (such as a wafer including a plurality of microelectronic devices), and a plating mask (such as can be provided using photolithographic techniques) can be used to expose portions of the underbump metallurgy layer on which solder bumps are to be grown. Electroplating is discussed, for example, in U.S. Pat. No. 6,117,299 entitled “Methods Of Electroplating Solder Bumps Of Uniform Height On Integrated Circuit Substrates” and in U.S. Pat. No. 5,293,006 entitled “Solder Bump Including Circular Lip”. Each of these patents is assigned to the assignee of the present invention, and the disclosures of each of these patents are hereby incorporated herein in their entirety by reference.
An electrode can be coupled to the continuous underbump metallurgy layer, a plating solution including the metal(s) to be electroplated can be provided, and an anode can be provided. By providing a plating current through the anode, plating solution, exposed portions of the underbump metallurgy layer, and the electrode, layers of the metal can be formed on exposed portions of the underbump metallurgy layer. The volume of the metal plated can be approximately proportional to the total charge of the plating current. Current control has thus been used in electroplating to provide deposition of a relatively uniform volume of metal. With current control, a fixed current can be applied to the plating solution over a fixed interval of time to provide a relatively uniform volume of plated solder.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, methods for electroplating metal can include passing an electrical current through a conductive surface and an electroplating solution adjacent the conductive surface. An electroplating voltage can be determined based on the electrical current through the conductive surface and the electroplating solution adjacent the conductive surface. The determined electroplating voltage can then be maintained while electroplating the metal from the electroplating solution on the conductive surface. By using an electrical current through the conductive surface and electroplating solution to determine an electroplating voltage, a more uniform electroplating rate (growth in thickness per unit time) may be provided. In addition, a more uniform plated metal may be provided.
A seed layer on a substrate can be covered with a plating mask that exposes portions of the seed layer on which solder bumps are to be plated. Sidewalls of the plating mask may have a slope so that a surface area of the bumps being plated increases as the thickness of the bumps increases. In addition, surface areas of the bumps may increase even more rapidly as the bumps “mushroom” outside the plating mask (i.e. grow over a top surface of the plating mask). By applying a fixed current during plating, the plating rate (growth in thickness per unit of time) may decrease as the exposed plating area increases. In sharp contrast, some embodiments of the invention may provide a constant plating rate which may provide a greater uniformity of the deposited metal layer.
REFERENCES:
patent: 5293006 (1994-03-01), Yung
patent: 6117299 (2000-09-01), Rinne et al.
patent: 6231743 (2001-05-01), Etherington
patent: 6440291 (2002-08-01), Henri et al.
patent: 6495018 (2002-12-01), Lowe
Solomon “Providing High Density and Performance for Chip-to System Interconnection” Advanced Packaging (Nov. 2001) pp 19-28.
Yung et al; “Flip-Chip Process Utilizing Electroplated Solder Joints”; Proceedings of the Technical Conference, (Sep. 10-12, 1990) International Electronics Packaging Conference Malborough, Massachusetts pp1065-1073.
Jones Curtis Grant
Rinne Glenn A.
Rogers William Boyd
King Roy
Leader William T.
Myers Bigel & Sibley & Sajovec
Unitive International Limited Curaco
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