Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2000-09-15
2002-02-05
Phasge, Arun S. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S157000, C205S264000, C205S266000, C205S291000
Reexamination Certificate
active
06344126
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system for electroplating the surfaces of semiconductor wafers and other workpieces. More particularly, the present invention relates to an electroplating apparatus and method that achieves improved performance with respect to thickness uniformity and rate of metal deposition.
BACKGROUND OF THE INVENTION
It is known to electroplate the surfaces of semiconductor wafers. It has been difficult, however, to obtain an electroplated layer of uniform thickness. It has been especially difficult to achieve the desired thickness uniformity at a high rate of metal deposition. Known systems for electroplating semiconductor products are described in U.S. Pat. No. 5,833,820 (Dubin), U.S. Pat. No. 5,670,034 (Lowery), U.S. Pat. No. 5,472,592 (Lowery), and U.S. Pat. No. 5,421,987 (Tzanavaras).
SUMMARY OF THE INVENTION
The present invention relates to an apparatus for electroplating a semiconductor product. The apparatus includes a support device for supporting the product in an electroplating solution, an electrical circuit for applying an electrical potential across the electroplating solution, and a control device for reducing the current distance to the product through the solution after an initial amount of conductive material is electroplated on the product surface. The semiconductor product may be, for example, a semiconductor wafer or chip. Integrated circuits may be formed in the product if desired.
According to one aspect of the invention, the support device includes conductive contacts. The contacts may be used to connect the product to the electrical circuit.
According to another aspect of the invention, the control device includes a mechanism for moving a metal target (anode) toward the electroplated product. In an alternative embodiment of the invention, the product may be moved toward the anode.
According to another aspect of the invention, a processor is used to operate the control device in response to data correlated to the electroplating process. The input data may be functionally related or correlated to elapsed electroplating time, the resistance of the product in the electroplating solution, the optical characteristics of the product, the surface capacitance of the product, etc.
The present invention also relates to a method of electroplating the surface of a semiconductor wafer. The method includes the steps of using an electrode to electroplate an initial amount of conductive material on the wafer surface, then changing the distance between the electrode and the wafer surface, and then using the electrode to electroplate an additional amount of material on the wafer surface. According to a preferred embodiment of the invention, at the start of the process, while the resistance of the wafer is significant, thickness uniformity is promoted by locating the target far from the wafer. Then, when the wafer resistance is reduced by the initial amount of electrodeposited metal, higher plating efficiency may be obtained by moving the target closer to the wafer.
According to another aspect of the invention, the wafer may be provided with a refractory seed layer. The seed layer contains metal and adheres to the semiconductor wafer material. The resistance of the seed layer is greater than that of the electrodeposited metal.
Thus, according to a preferred embodiment of the invention, a metal target (anode) is located relatively far from the wafer (cathode) at the beginning of the plating process, until a sufficient amount of metal is plated on the wafer surface. Once the metal is built up on the wafer surface, the target is moved closer to the wafer for faster processing.
As explained in more detail below, before the metal is built up on the wafer surface, the high resistance of the seed layer is a significant factor. The electrical potential near the contacts on the edges of the wafer is greater than the potential at die center of the wafer. Consequently, according to the invention, the target and the wafer are separated from each other to increase the resistance of the electroplating solution (the bath). A relatively high bath resistance mutes the significance of the potential difference in the radial direction of the wafer. Metal built up on the wafer surface has less resistance than the seed layer, such that the difference in potential across the surface of the wafer becomes less significant. Eventually, the target can be moved closer to the wafer (to reduce the bath resistance and increase the deposition rate) without impairing plating uniformity.
These and other features and advantages of the invention will become apparent from the following detailed description of preferred embodiments of the invention.
REFERENCES:
patent: 3746633 (1973-07-01), Miyato et al.
patent: 3887452 (1975-06-01), Mannaka et al.
patent: 4098666 (1978-07-01), Ralston
patent: 4287043 (1981-09-01), Eckert et al.
patent: 4497695 (1985-02-01), Shinkai et al.
patent: 5421987 (1995-06-01), Tzanavaras et al.
patent: 5472592 (1995-12-01), Lowery
patent: 5670034 (1997-09-01), Lowery
patent: 5833820 (1998-11-01), Dubin
patent: 6217727 (2001-04-01), Moore
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Phasge Arun S,.
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