Electroplated wire layout for package sawing

Details Electroplated wire layout for package sawing Electroplated wire layout for package sawing

2006-08-29

2006-08-29

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257S776000, C257S692000, C257S773000

Reexamination Certificate

active

07098524

ABSTRACT:
An electroplated wire layout for package sawing comprises a substrate with a plurality of chip arrays disposed thereon. A kerf having two scribe lines is disposed between every two chip arrays. Several solder ball pads corresponding to the chip arrays are disposed on a back surface of the substrate. Each solder ball pad has a solder ball electroplated wire extended into a kerf. There is also a kerf electroplated wire disposed in each kerf and above the scribe lines of the kerf in a zigzag way. The kerf electroplated wire is connected with the solder ball pad electroplated wires to achieve electric connection. By changing the shape of the kerf electroplated wire, the kerf electroplated wire can be easily cut off to enhance the yield and reliability and also lower the cost.

REFERENCES:
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 6730989 (2004-05-01), Reithinger et al.

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