Electronically erasable-programmable memory cell having buried b

Details Electronically erasable-programmable memory cell having buried b Electronically erasable-programmable memory cell having buried b

1993-05-20

1996-04-16

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

257315, 257316, G11C 700, H01L 29788

Patent

active

055089550

ABSTRACT:
A memory cell (510) suitable for an array of memory cells (100) has a source that is part of a buried bit line and a drain that is part of an adjacent buried bit line. The memory cell also includes a split gate arrangement (580) in which the gate is integral with the word line (120), with a part of the gate being the control gate of an EEPROM transistor which erases and programs on the principle of Fowler-Nordheim tunneling (560, 570), and another part of the gate being the control gate of a series select transistor. The memory cell is erased by placing a voltage on the word line which is positive relative to the bit line and the substrate and of sufficient magnitude to cause tunneling. The memory cell is programmed by placing a negative voltage on the word line and a voltage corresponding to the logical value on the bit line. The bit line voltage is sufficient to cause tunneling for one logical value, and insufficient to cause tunneling for the other logical value. The memory cell is read by placing a sense voltage across the bit lines forming its source and drain, and a read voltage on the control gate. Other bit lines are left floating.

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Paper entitled, "A 128K Flash EEPROM Using Double-Polysilicon Technology", written by Gheorghe Samachisa, et al, reprinted from IEEE J. Solid-State Circuits, vol. SC-22, No. 5, pp. 676-683, Oct. 1987, IEEE Log Number 8716433, pp. 176-182.
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