1976-07-15
1977-12-13
Weldon, Ulysses
58 855, G04B 2708
Patent
active
040621782
ABSTRACT:
A frequency regulating circuit for an electronic timepiece is provided. The electronic timepiece includes an oscillator circuit for producing a high frequency time standard signal and a divider circuit for producing a low frequency timekeeping signal in response to the high frequency time standard signal being applied thereto. The divider circuit includes a plurality of series-connected divider stages, the frequency of the low frequency timekeeping signal being determined by the number of divider stages. Each divider stage is adapted to produce an intermediate frequency signal representative of the count thereof. The frequency regulating circuit is particularly characterized by a first logic circuit adapted to receive certain of said intermediate frequency signals produced by the divider stages and in response to a coincident binary state of the intermediate frequency signals applied thereto, apply a control signal to each of the divider stages to adjust the count of each of the divider stages to the same binary state. A gating circuit is coupled intermediate each of the divider stages and the logic circuit and is adapted to select the manner in which certain of the intermediate frequency signals are applied to the logic gate and thereby regulate the frequency of the low frequency timekeeping signal.
REFERENCES:
patent: 3540207 (1970-11-01), Keeler
patent: 3777471 (1973-12-01), Koehler et al.
patent: 3812669 (1974-05-01), Wiget
patent: 3895486 (1975-07-01), Hammer et al.
Kabushiki Kaisha Suwa Seikosha
Weldon Ulysses
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