Electronic system with circuitry for generating memory column ad

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395307, 39549703, 36523006, G06F 1200, G11C 800

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active

057245533

ABSTRACT:
An electronic system including circuitry for generating column addresses for a memory in the system, based upon signals on an address bus in the system, is disclosed. The disclosed system includes a microprocessor unit having a memory controller unit, within which circuitry for receiving address lines from the address bus, and for receiving control register bits indicating a particular memory array type, is provided. The memory array type indicates the number of the address bits which are to be forwarded to the memory as the column address, rather than as the row address. The memory is of a dynamic random access (DRAM) type, for which row and column addresses are time-multiplexed over the same lines. The microprocessor unit may be integrated onto a single integrated circuit chip with the memory controller, and may include a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes circuitry for controlling the access to configuration registers, and circuitry for determining the sizes of individual memory banks in the memory.

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