Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-08-27
2001-04-24
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S285000, C327S270000, C327S281000, C327S261000, C327S384000, C326S083000, C326S027000, C326S121000
Reexamination Certificate
active
06222396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic systems and more particularly relates to multiple output buffer drivers stages.
2. Description of the Related Art
An integrated circuit output buffer circuit typically charges and discharges an output impedance network that includes, for example, integrated circuit package leads and other large and small impedances connected to the leads. Rapid current changes associated with charging and discharging of the impedance network may produce power supply voltage noise when parasitic reactances and reactive loads are driven by the output buffer. This power supply voltage noise is undesirable because, if a large enough voltage swing occurs, it can be interpreted as an input signal state change by loads connected to the leads.
A network formed by the output buffer, a load connected to integrated circuit package leads, and a conductive path between the power supply voltage source and the load can be represented by an RLC equivalent circuit. When driving complimentary metal oxide semiconductor (CMOS) circuitry, the inductance, L, is generally due to the inherent parasitic self inductance of the leads and conductive path. The capacitance (C) is generally due to the capacitive load of circuitry connected to the leads, and the resistance, R, is generally the resistance of the conductive path.
As loads are driven to HIGH voltages, e.g., 2-3.3 volts (V), and to LOW voltages, e.g., 0-1 V, by the output buffer, current varies over time at a rate defined by dI/dt, the derivative of output current over time. Power supply voltage noise is a function of dI/dt and the network impedance and can cause unintentional logic level changes in logic devices connected to the leads if the out buffer output voltage amplitude exceeds a logical threshold of the logic device. Power supply voltage noise may be manifested on a line supplying power to the output buffer and other circuits. The power supply line is often distributed around an integrated circuit periphery, and other circuits, such as an input buffer circuit sharing the same power line, may experience voltage instability due to the supply voltage noise. A noisy supply voltage may also cause logic shifting of data driven to a voltage level by other bus drivers sharing the same power line as the output buffer circuit causing the large dI/dt.
Conventionally, attempts have been made to reduce dI/dt by introducing resistance into the current path of a driving transistor. However, this may not sufficiently reduce dI/dt induced noise appearing on supply voltage lines, Vsso and Vcco, especially for coincident switching output buffers. Another attempted solution increases the number of power supply pins to a circuit to distribute current paths and thus reduce aggregated dI/dt. However, the number of supply pins may be constrained by, for example, a need for backwards compatibility or a need to utilize available pins for other purposes.
Accordingly, a need exists for an output buffer that sufficiently reduces dI/dt induced noise, including power supply voltage noise, in all modes of operation.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, output buffer drivers of a multistage output buffer driver system transition from an OFF state to an approximately saturated state during approximately mutually exclusive periods of time. The state transition of each of the output buffer drivers causes dI/dt induced noise. However, because the state transitions occur during approximately mutually exclusive periods of time, an aggregate dI/dt during any period of time is substantially attributable to only one output buffer driver. Furthermore, in one embodiment, smaller output buffer drivers are used in initial stages to reduce dI/dt. Additionally, state transition times are regulated by delay circuits which control the output buffer drivers so as to further control dI/dt.
In one embodiment, two banks of multistage delay circuitry and associated output drivers supply current from a power supply having terminals at different voltage potentials and regulate associated output buffer driver state transition times. The respective banks operate similarly with one bank causing associated output buffer drivers to source current to a load and the other bank causing associated output buffer drivers to sink current from a load. A signal source control signal causes one bank delay circuits to substantially simultaneously turn OFF (nonconducting) associated multistage output buffer drivers. Simultaneously, another control signal from the signal source causes a first delay stage to relatively slowly charge transition an output control signal so as to turn ON an associated output buffer driver. The delay stages are “daisy chained” so that the second delay stage responds to the output control signal of the first delay stage by transitioning the second delay stage output control signal, the third delay stage likewise responds to the output control signal of the second delay stage, and so on for X delay stages. Each delay stage includes resistive elements that delay the transition of a respective output control signal for a predetermined period of time when the output control signal of a delay stage is being used to turn an output buffer driver ON (conducting). Each delay stage also includes elements of relatively LOW resistivity that are used to relatively quickly transition a respective output control signal to a state to turn a respective output buffer driver OFF. The delay between respective output control signal transitions which control respective output buffer driver state transitions provides the approximately mutually exclusive output buffer driver transition to saturation periods and provides the LOW dI/dt relative to conventional quick transition, simultaneous turn ON output buffer drivers.
In another embodiment, the number of active stages may be selected by, for example, a programmable register. Thus, the number of conducting output buffer drivers can be limited in accordance with, for example, connected load current requirements, to further limit total dI/dt noise and reduce power consumption of, for example, an electronic communication system such as a mobile telephone. By limiting the dI/dt noise, inadvertent circuit device logic level changes can be reduced or eliminated which, for example, increases the reliability of the electronic system employing the multistage output buffer system.
In another embodiment of the present invention, an electronic system includes a plurality of delay stages, each delay stage having a first control signal input terminal to receive a first input control signal and having a first control signal output terminal to provide a first output control signal in delayed response to receipt of the first input control signal, wherein the first control signal input terminal of each delay stage, except for the first delay stage, is coupled to the first control signal output terminal of another respective delay stage, and the first control signal input terminal of the first delay stage is for receiving a first input control signal from a signal source. The electronic system further includes a plurality of output buffer drivers coupled to a respective delay stage, each output buffer driver having a first control terminal to receive the first output control signal from one of the respective delay stages and having a first output terminal for coupling to a load.
In another embodiment of the present invention, a method includes the steps of receiving an input control signal and providing a first output control signal to a first output buffer driver. The method further includes the steps of providing an ith output control signal to an ith output buffer driver in delayed response to the (i−1)th output control signal, wherein i is an integer ranging from 2 to N, and N is an integer greater than or equal to 2 and repeating the step of providing an ith output control signal to an ith output buffer until an output control signal is provided to each of N
Le Dinh T.
Legerity Inc.
Skjerven Morrill & MacPherson LLP
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