Electronic stream processing circuit with locally controlled...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing

Reexamination Certificate

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C716S108000

Reexamination Certificate

active

07900171

ABSTRACT:
A receiver circuit has a chain of stream processing circuits (10a-c)—having control parameter inputs for receiving control parameter values. To facilitate design of circuits that receive data with a variable block size, an included control circuit (14) selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions specifying the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c). Each local control circuit (11) receives at least part of the instructions and applies parameter values from the instructions to its corresponding stream processing circuit (10a-c). The local control circuit (11) controls timing of control parameter updates using block sizes from the instructions.

REFERENCES:
Hasan et al., “A delay spread based low power reconfigurable FFT processor architecture for wireless receivers,” 2003 Proceedings Int'l Symposium on System-on-Chip, p. 135-138.
Swanchara et al., “A methodical approach for stream-oriented configurable signal processing,” 1999 Proceedings 32nd Annual Hawaii int'l Conference on System Sciences, pp. 3-4.
Zhang et al., “Architectural evaluation of flexible digital signal processing for wireless receivers,” 2000 Record of 34th Asilomar Conference on Signals, Systems and Computers, pp. 78-83.
Mohebbi et al., “A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core,” 2003 IEEE, pp. 103-108.

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