Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
2000-01-25
2001-04-24
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S566000, C257S570000
Reexamination Certificate
active
06222248
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an electronic semiconductor device having a modified insulated gate bipolar transistor with integrated diode.
BACKGROUND OF THE INVENTION
A known electronic device is a transistor of the type called IGBT (Insulated Gate Bipolar Transistor). IGBT devices are components used in power applications as an alternative to bipolar junction transistors (BJT) or field-effect power transistors, such as vertical conduction transistors, known as VDMOS (Vertical Double diffused Metal Oxide Semiconductor) transistors. They are sometimes preferred to BJT and VDMOS transistors because they have a smaller size with the same electrical performance. In some applications, however, VDMOS transistors are more advantageous than IGBT devices because they contain, as a component intrinsic to their structure, a reverse diode between the drain and source. A typical application in which this characteristic of the VDMOS is exploited is that in which the power device is used as an electronic switch in a bridge or half-bridge circuit configuration. In this configuration, the diode allows current to flow when the power device is biased in the reverse conduction direction. If an IGBT is to be used as an electronic switch in this circuit configuration, it is necessary to connect a separate diode between its emitter and collector terminals. This results in a greater complexity of construction and a larger size of the whole device.
It has been proposed that an IGBT be modified in such a way that a structure normally present in this device is used as a reverse diode. An IGBT modified in this way is described below in relation to FIG.
1
.
FIG. 1
shows in section an edge portion of a chip
9
of semiconductor material, for example monocrystalline silicon. The chip
9
comprises a substrate
10
doped with P type impurities in a relatively high concentration, and consequently denoted by P+, an epitaxial layer
11
doped with N type impurities in a relatively low concentration, and consequently denoted by N−, and an N+ “buffer” layer
12
between the substrate
10
and the epitaxial layer
11
. (The buffer layer may also be absent in certain types of IGBT). A diffused P type region
13
extends from the front surface of the chip
9
into the epitaxial layer
11
and is formed by a low-concentration (P−) surface part
13
′ and a highconcentration (P+) deep part
13
″. Another P type region, indicated by
14
, also formed by a low-concentration part
14
′ and a high-concentration part
14
″, is shaped in such a way that it surrounds the region
13
.
High-concentration N type regions
15
are formed in the regions
13
and
14
. Strips of electrically conducting material, for example doped polycrystalline silicon, indicated by
16
, separated from the front surface of the chip by a thin layer of dielectric material, for example silicon dioxide, are located above the surface areas of the regions
13
′ and
14
′ lying between the regions
15
and the epitaxial layer
11
. The strips
16
are joined together (in a way not shown in the drawing) in a structure which also comprises a contact portion
16
′. A metallic electrode
17
in contact with the bottom surface of the chip, in other words with the free surface of the substrate
10
, forms the collector electrode C of the transistor. A metallic electrode
18
in contact, on the front surface, with the P+regions
13
and
14
and with the N+regions
15
, but insulated from the strips
16
by layers of dielectric material
19
, for example silicon dioxide, forms the emitter electrode E of the IGBT. A metallic electrode
20
in contact with the contact portion
16
′ forms the gate electrode of the IGBT.
It should be noted that two separate electrodes, one in contact with the region
13
and one in contact with the region
14
, but connected electrically to each other by a suitable connecting element, could be provided instead of a single electrode
18
in contact with the regions
13
and
14
. A further metallic electrode
21
forms an ohmic contact with the epitaxial layer
11
through a diffused high-concentration N type surface region, indicated by
22
, and is shaped in the form of a frame extending close to the edge of the chip. This electrode is also connected, by a conductor external to the chip
9
, to the collector electrode
17
of the IGBT.
FIG. 2
shows in a plan view, and not to scale, the chip
9
fixed to a metallic support
23
and connected electrically to three terminals of the device. More in particular, one of the three terminals, indicated by
24
, is soldered to the metallic support
23
, the collector electrode
17
is soldered to the metallic support
23
and is therefore connected electrically to the terminal
24
, the emitter electrode
18
and the gate electrode
20
are connected by corresponding metal wires to the other two terminals
25
and
26
, and the electrode
21
is connected by a wire to the terminal
24
.
In operation, when a potential which is positive with respect to that of the emitter is applied to the collector, and the gate electrode is biased, with respect to the emitter electrode, at a potential greater than the conduction threshold level, a current flows from the emitter to the collector, as indicated by arrows in the Figure. Conversely, when the gate electrode is biased at a potential lower than the conduction threshold level, no current passes between the emitter and the collector and the device therefore acts as an open switch. The maximum voltage that can be applied between the collector and the emitter is determined by the breakdown voltage of the junctions which the regions
13
and
14
form with the epitaxial layer
11
. The region
14
surrounds the whole active region of the device in the same way as a frame, and its low-concentration surface part
14
′ which extends laterally towards the edge of the chip makes it possible to obtain a breakdown voltage close to the theoretical level, owing to the known effect of reduction of the density of the field lines at the surface. The electrode
21
, which is not normally connected to the collector electrode, is used to keep the whole edge area of the chip at the same potential, and is therefore usually called an equipotential ring or EQR. This has the effect of maintaining a uniform breakdown voltage over the whole chip. The combination of the region
14
and the electrode
21
is normally called an edge structure or a termination structure.
Since the electrode
21
is connected to the collector C, when the IGBT is reverse-biased, in other words when the collector has a negative potential with respect to the emitter, the diode formed by the p-n junction between the region
14
and the epitaxial layer
11
, in other words between the emitter electrode and the electrode
21
, indicated by D in
FIG. 1
, is conducting. The IGBT can therefore be used in a bridge or in a half-bridge in the applications described above.
However, it has been found that the diode thus formed has a high resistance in forward conduction, and therefore the voltage drop across its terminals is high even with relatively low currents, for example more than 5 V for a current of 0.4 A, whereas a drop of approximately 2 V, like that of the IGBT in forward conduction, would be desirable. Moreover, the characteristics of the diode cannot be improved beyond a certain limit because they depend on parameters which cannot be modified without altering the characteristics of the IGBT, such as the perimeter of the termination region
14
, the distance between the EQR electrode
21
and the P+ part
14
″ of the region
14
, and the width of the P−region
14
′.
SUMMARY OF THE INVENTION
The present invention provides an electronic device of the type described above having an integrated diode with operating characteristics.
REFERENCES:
patent: 5012313 (1991-04-01), Fijihira
patent: 5365085 (1994-11-01), Tokura et al.
patent: 5777367 (1998-07-01), Zambrano
pa
Chaudhuri Olik
Galanthay Theodore E.
Pham Hoai
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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