Electronic postage meter having redundant memory

Details Electronic postage meter having redundant memory Electronic postage meter having redundant memory

1990-11-28

1992-04-28

Shaw, Gareth D.

Excavating

371 681, 364DIG1, 364DIG2, 3642685, 3649442, G06F 1116

Patent

active

051095076

ABSTRACT:
An electronic postal meter has an accounting unit with redundant nonvolatile random access memories controlled by a microprocessor system. The redundant random access memories have separate groups of address and data lines to minimize identical errors in data stored therein. The data transfer may occur at different times to and from the memories, with respect to any given byte of data. The system may incorporate redundant microprocessors, and critical parameters may be checked at periodic intervals in the main program of the accounting microprocessor system.

REFERENCES:
patent: 3252149 (1966-05-01), Weida et al.
patent: 3311890 (1963-08-01), Waaben
patent: 3544777 (1970-12-01), Winkler
patent: 3668644 (1972-01-01), Looschen
patent: 3938095 (1976-02-01), Check, Jr. et al.
patent: 3978327 (1976-08-01), Huber
patent: 3978457 (1976-08-01), Check, Jr. et al.
patent: 4012717 (1977-03-01), Censier et al.
patent: 4093999 (1978-06-01), Fuller et al.
patent: 4301507 (1981-11-01), Soderberg et al.
patent: 4313200 (1982-01-01), Nishiura
patent: 4358823 (1982-11-01), McDonald et al.
patent: 4375678 (1983-03-01), Krebs, Jr.
patent: 4422140 (1983-12-01), Keats
patent: 4422148 (1983-12-01), Soderberg et al.
patent: 4481604 (1984-11-01), Gilham et al.
patent: 4484307 (1984-11-01), Quatse et al.
patent: 4916623 (1990-04-01), Check, Jr.
Chamoff et al., "Non-Volatile Total Implementation", IBM Technical Disclosure Bulletin, vol. 20, No. 10, Mar. 1978, pp. 4071-4072.
Hackl et al., "Dynamic Allocation of High Availability Storage", IBM TDB, vol. 10, No. 10, Mar. 1968, pp. 1484-1485.
Katsuki, D., et al., "Pluribus--An Operational Fault-Tolerant Multiprocessor," IEEE Proceedings, vol. 10, No. 10 (Oct. 1978).
Szygenda, S. A., et al., "Self-Diagnosis and Self-Repair in Memory: An Integrated Systems Approach", IEEE Transactions on Reliability, vol. R-22, No. 1 (Apr. 1973).
Depledge, P. G., "Fault-Tolerant Computer Systems", IEEE Proceedings A, vol. 128, No. 4 (Oct. 1981).
Irwin, J. W., "Microprocessor Error Layout", IBM Technical Disclosure Bulletin, vol. 18, No. 4, Sep. 1975, pp. 1011-1013.

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