Electronic postage meter having memory write access second chanc

Details Electronic postage meter having memory write access second chanc Electronic postage meter having memory write access second chanc

1993-02-10

1995-08-01

Beausoliel,, Jr.

Boots, shoes, and leggings

371 62, 36491552, 395550, G06F 1520

Patent

active

054385199

ABSTRACT:
A postage meter control system includes a microcomputer having a programmable microprocessor. The microcomputer is in communication with a decoder integrated circuit (Decoder IC). The Decoder IC has a first write control flip-flop and a second write control flip-flop, as in the preferred embodiment there are redundant non-volatile memories. Each control flip-flop has an output to a respective AND gate. The Decoder IC includes a dual timer which has an output to the control flip-flops. As a result, when the microcomputer enters write routine, the timer releases the control flip-flops to allow the system to be write enabled. If the write routine encounters a error, resulting in the timer timing out, the timer resets the control flip-flop and communicates with the microcomputer to try a retry. A more detailed description, and other features and advantages will become apparent in conjunction with the detailed description of the preferred embodiment.

REFERENCES:
patent: 4584647 (1986-04-01), Eckert
patent: 4701856 (1987-10-01), DiGiulio et al.
patent: 4710882 (1987-12-01), DiGiulio et al.
patent: 4742469 (1988-05-01), Haines et al.
patent: 4837702 (1989-06-01), Obrea
patent: 4998203 (1991-03-01), DiGiulio et al.
patent: 5260900 (1993-11-01), Muller

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