Electronic parts packaging structure and method of...

Details Electronic parts packaging structure and method of... Electronic parts packaging structure and method of...

2006-06-06

2006-06-06

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S778000, C257S787000, C257S723000, C257S686000

Reexamination Certificate

active

07057290

ABSTRACT:
An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

REFERENCES:
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5780776 (1998-07-01), Noda
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 2001/0004130 (2001-06-01), Higashi et al.
patent: 2000-323645 (2000-11-01), None
patent: 2001-177045 (2001-06-01), None

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