Electronic package with integrated clock distribution structure

Details Electronic package with integrated clock distribution structure Electronic package with integrated clock distribution structure

2003-05-22

2004-04-13

NuTon, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S141000

Reexamination Certificate

active

06720814

ABSTRACT:

BACKGROUND
1. Field
This invention relates generally to clock signal distribution. More specifically, this invention relates to a system and method for spatial clock signal distribution using an electronic package.
2. General Background and Related Art
In microelectronic chips such as microprocessors, the operations of multiple chip components must be synchronized. Yet, the physical separation of such components may cause significant propagation delay-induced phase shifts. In recent years, the operating frequency, or clock frequency, of microprocessors has steadily risen. Because of such increases in clock frequency, as well as increased system function, problems relating to high-frequency effects and power consumption have become more pronounced. As such, clock distribution techniques have been proposed to minimize these effects.
A number of clock distribution techniques have involved propagating clock signals in order to synchronize the signals at receiving points. For example, clock signals are generated on-chip using microchip transmission lines
10
arranged on a microelectronic chip in a so-called H-tree, as shown in
FIG. 1
(Prior Art). The purpose of the H-tree structure is to minimize skew due to different path lengths from a clock generator
20
to the various receiving elements. Propagation loss and repeated branching at T-junctions
30
generally require the introduction to a microelectronic chip of clock buffers
40
that receive and retransmit a clock signal along a path from the clock generator
20
to any particular clock receiver
50
. In some systems that include H-tree structures, a clock signal could traverse, for example, as many as ten stages of clock buffers before reaching its final destination. Because of the large number of such elements, skew, jitter, and excessive power consumption result.
Standing-wave behavior is characterized by discontinuous progression or abrupt jumps in the advancement of phase with distance. This behavior is a fundamental property of standing waves in any physical situation governed by the wave equation and where the signal is isophasic, that is, its phase remains constant over extended regions and abruptly jumps by 180° between adjacent regions. A clock distribution technique has attempted to exploit the spatial phase characteristics of a standing wave to minimize clock skew. In particular, standing waves are generated on a semiconductor die and extended to clock receivers at various entities to be synchronized. However, amplifiers and phase advancing units must be employed along transmission paths to minimize losses.
Therefore, what is needed is an improved system and method for distributing a clock signal.


REFERENCES:
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patent: 5387885 (1995-02-01), Chi
patent: 5640112 (1997-06-01), Goto et al.
“RF Interconnect for Multi-Gbit/s Board-Level Clock Distribution”, Woonghwan Ryu, et al., IEEE Transactions on Advanced Packaging, vol. 23, No. 3, Aug. 2000, pp. 398-407.
“Salphasic Distribution of Clock Signals for Synchronous Systems”, Vernon L. Chi, IEEE Transactions on Computers, vol. 43, No. 5, May, 1994, pp. 597-602.
“Wave Model Solution to the Ground/Power Plane Noise Problem”, Guang-Tsai Lei, et al., IEEE Transactions on Instrumentation and Measurement, vol. 55, No. 2, Apr., 1995, pp. 300-303.
“High-Frequency Characterization of Power/Ground-Plane Structures”, Guang-Tsai Lei, et al., IEEE Transactions on Microwave Theory and Techniques, vol. 47, No. 5, May, 1999, pp. 562-569.
“Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials”, R. Emery, et al., Intel Corporation.
“Bumpless Build-Up Layer Packaging”, Steven N. Towle, et al., Intel Corporation.

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