Electronic package with enhanced pad design

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

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361764, 361767, 361772, 361773, 361774, 361777, 361783, 361784, 257684, 257690, 257692, 257735, 257738, 257774, 257778, 257780, 257782, 257784, H01L 2500, H05K 118

Patent

active

058256288

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to an electronic package and particularly, but not exclusively, to an electronic package including a substrate and at least one device, each of said at least one device being attached to said substrate by means of a conductive pad provided on a surface of said substrate.
An electronic package typically includes a circuitized substrate with one or more active devices attached thereon; packages including only one device are known as Single Chip Modules (SCM), while packages including a plurality of devices are called Multi Chip Modules (MCM). The use of attach materials, such as a glue, is common in electronic packaging applications for attaching the devices to the substrate, particularly in Ball Grid Array (BGA) packages.
BGA packages are a quite recent development in the electronic packaging industry replacing the current products as the Quad Flat Packs (QFP). The main difference is the connection system to the printed circuit board (PCB), also called second level attachment, that is made through eutectic Tin Lead alloy balls arranged in a matrix layout on the bottom side of a substrate, instead of metal leads placed along the peripheral corner of the plastic component body. BCA and QFP packages are described in "Circuits Assembly (U.S.A.)--Vol.6, No.3 March 1995 Pag.38-40".
Each device is commonly attached to the substrate by means of a conductive pad, typically a little bigger that the corresponding attached device, provided on the top surface of the substrate. These pads provide a better compatibility with the glue material; in addition, they facilitate for some extent the heat transfer from the back of the device into the substrate by conduction.
A drawback of the prior art is that each pad causes a waste of a big area on the top surface of the substrate that cannot be wired and then it is not at all available for the routing of connecting lines. This problem is particularly serious in a Multi Chip Module, wherein the wasted area not available for wiring has to be multiplied by the number of devices. This problem involves increasing the electronic package dimensions or reducing the number of devices installed on the same substrate, increasing the number of modules required for the same application.
In order to increase the wireability of the electronic package, a current methodology it that of sacrifying the pad and using the freed area of the substrate for wiring; however, this solution causes a degradation of the thermal performances of the package, particularly in organic substrates, with a value of thermal dissipation typically not greater than 0.5 W. A different approach is to modify the substrate, either changing the raw-materials and technologies toward more conductive ones, like ceramic carriers, or increasing the number of layers thereof; both solutions however are more expensive and increases the cost of the whole package.
A further problem is that these modules, as any other electronic components, need to be decoupled with capacitors to reduce signal noise either at the application board level or at module substrate.
The signal noise optimisation is usually addressed bridging with capacitors power and ground as close as possible to the active device. When these capacitors are on board at the package level, they require a specific wiring pattern and than impact the already small real estate available for the circuitry, enlarging consequently the total module dimensions. On the contrary, when the capacitors are assembled on the mother board where the modules are, they provide very often a barely acceptable level of noise reduction.


BRIEF SUMMARY OF THE INVENTION

The above drawbacks of the prior art are overcome by the invention as claimed. Accordingly, the present invention provides an electronic package as set out above which is characterised in that said pad is composed by a plurality of parts not in contact.
This solution allows solving both the above mentioned problems. Particularly, it allows increasing the electrical wireabili

REFERENCES:
patent: 4578573 (1986-03-01), Flies et al.
patent: 4595945 (1986-06-01), Graver
patent: 4714952 (1987-12-01), Takekawa et al.
patent: 5229846 (1993-07-01), Kozuka
patent: 5258648 (1993-11-01), Lin
patent: 5285352 (1994-02-01), Pastore et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5389817 (1995-02-01), Imamura et al.
patent: 5468999 (1995-11-01), Lin et al.
patent: 5474958 (1995-12-01), Djennas et al.
W.E. Bernier, B.T. Ma, P.A. Mescher, A.K. Trivedi and E.J. Vytlacil, "BGA vs. QFP", Circuits Assembly (USA) vol. 6, No. 3, Mar. 1995, pp. 38-40.

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