Electronic package structure and the packaging process thereof

Details Electronic package structure and the packaging process thereof Electronic package structure and the packaging process thereof

2005-01-03

2008-10-21

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S735000

Reexamination Certificate

active

07439619

ABSTRACT:
The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.

REFERENCES:
patent: 5708294 (1998-01-01), Toriyama
patent: 6670222 (2003-12-01), Brodsky

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