Electronic package for high density integrated circuits

Details Electronic package for high density integrated circuits Electronic package for high density integrated circuits

1980-06-02

1981-10-20

Kucia, Richard R.

Electricity: electrical systems and devices

Miscellaneous

174 52S, 361412, 361421, H05K 114

Patent

active

042964563

ABSTRACT:
The present disclosure describes a multi-layered integrated circuit package especially suited for high density circuit applications, such as those involving LSI or ULSI. The package is characterized by short uninterrupted electrical circuit paths between the integrated circuit chip and an interconnection medium. The use of metallized vias or feed-throughs commonly employed in multi-layered packages have been eliminated. Also, heat dissipation is enhanced by the short thermal path between the chip and the outer package surface. Finally, the signal lead configuration permits the area occupied by the package on the interconnection medium to be significantly less than that of present-day packages having approximately the same number of input/output pins or terminals.

REFERENCES:
patent: 3337678 (1967-08-01), Stelmak
patent: 3354394 (1967-11-01), James
patent: 3374537 (1968-03-01), Doelp
patent: 3550766 (1970-12-01), Nixen
patent: 3676748 (1972-07-01), Kobayashi et al.
patent: 3701964 (1972-10-01), Cronin
patent: 3760090 (1973-09-01), Fowler
patent: 3781596 (1973-12-01), Galli
patent: 3809797 (1974-05-01), McMunn
patent: 4164003 (1979-08-01), Cutchaw
patent: 4225900 (1980-09-01), Ciccio
Holsopple et al., Increased Useable I/O Pins on a Substrate, IBM Tech. Disc. Bull., v. 23 #7A, Dec. 1980, pp. 2716 & 2717.
Caccoma et al., Standardized Mulilayer Pin-Lead Frame Contactor, IBM Tech. Disc. Bull., v. 16 #3, Aug. 1973, pp. 991 & 992 relied on.

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