Electronic package

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357 80, G11C 504, H01L 2302

Patent

active

049965859

ABSTRACT:
An electronic package (11) which comprises a substrate (12) having several chips (13) arranged thereon, and a plurality of connector pins (26) fitted in pin plates (21-24) and electrically connected via conductors to the chips (13). Each pin plate is mounted by means of at least one flexible connector element (29) connected to the conductors at a respective peripheral section (16-19) of the substrate (12). The pin plates have a base surface in the form of any discretionary polygon, in such a manner that, when folded, form a plane substantially flush with the plane of the substrate (12) into a position beneath the substrate (12), or vice versa. Thus an electronic package is obtained which is less complex in its manufacture and covers a considerably reduced base surface while offering a comparable performance.

REFERENCES:
patent: 3877064 (1975-04-01), Scheingold et al.
patent: 4126882 (1978-11-01), Carson et al.
patent: 4377854 (1983-03-01), Braun et al.
patent: 4420877 (1983-12-01), McKenzie, Jr.
patent: 4742024 (1988-05-01), Sugimoto et al.
patent: 4916523 (1990-04-01), Sokolovsky et al.
"Silicon-on-Silicon Packaging", R. K. Spielberger et al.; IEEE, vol. CHMT-7, No. 2, Jun. 1984, pp. 193-196.
"Compact Low Profile VLSI IC Package", A. R. Gresko, IBM Technical Disclosure Bulletin, vol. 24, No. 12, May, 1982, pp. 6388-6389.

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