Electronic output stage

Amplifiers – With periodic switching input-output

Reexamination Certificate

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C330S252000, C330S253000

Reexamination Certificate

active

06781449

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the fields of electronics and electronic circuits. More specifically, the invention relates to an electronic output stage, particularly to an output stage for CMOS LVDS (Low Voltage Differential Signaling) levels for use in analog and digital high-frequency circuits.
The publication “Makrozellen für serielle Gbit/s Schnitt-stellen in 0.35 &mgr;m CMOS” (Tagungsband 8, ITG Fachtagung 3.-4.3.98 Hannover, pp.107-112, ITG Fachbericht 147) describes a circuit for an electronic output stage for digital signals with a large-signal control. The output stage comprises a controlled push-pull stage whereby a high-level signal and a low-level signal can be independently controlled. The control is carried out i) individually for the high and low levels by means of analog control voltages from a reference block and a digital scaling, or ii) only by means of digital scaling. The digital scaling can be set by way of a computer interface. The prior art circuit has the disadvantage that a full CMOS swing (e.g., 3.3. or 5 Volts) and an expensive control for the bias currents of the provided differential amplifier stages are needed for drive purposes. In the prior art circuit, the transistors of the electronic output stages are used as switches, and therefore they can be operated in an unsaturated state.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electronic output stage for CMOS LVDS levels which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the electronic output stage can be driven with small signals, preferably with high-frequency small signals.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electronic output stage for amplifying differential input signals with a small voltage swing, in particular high-frequency input signals. The novel output stage comprises:
a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a controlled current source;
a first transistor having a first terminal connected to the controlled current source, a second terminal, and a control terminal connected to the first input terminal;
a second transistors having a first terminal connected to the controlled current source, a second terminal, and a control terminal connected to the second input terminal;
a third transistor having a first terminal connected to a first supply voltage potential, a second terminal connected to the second terminal of the first transistor and to the first output terminal;
a fourth transistor having a first terminal connected to the first supply voltage potential, a second terminal connected to the second terminal of the second transistor and to the second output terminal;
the control terminals of the third and fourth transistors receiving respective drive signals formed from the input signals by amplifying and providing the input signals with an adjustable offset voltage; and
wherein a voltage change of the input signals and drive signals at the first and third transistors and at the second and fourth transistors, respectively, behave in opposite ways.
In accordance with an added feature of the invention, at least one of the output voltages of the output terminal is adjustable with the offset voltage, and a current flowing through the first and second output terminals and an output resistance is adjustable with the current source and a dimensioning of the third and fourth transistors.
In accordance with an additional feature of the invention, the first and second transistors have equal dimensions, and the third and fourth transistors have equal dimensions. Preferably, also, the first, second, third, and fourth transistors are all MOS transistors.
In accordance with another feature of the invention, there is provided a differential amplifier circuit for setting the offset voltage such that the third and fourth transistors are at least partly conductive.
In accordance with a further feature of the invention, the current source is set such that an output current equals approximately 3.5 mA. The third and fourth transistors are preferably dimensioned such that an output resistance between the first and second output terminals equals approximately 50 ohms. That is, with suitable dimensioning of the electronic elements of the output stage, it is possible to realize an output resistance of approx. 50 ohms, which is required by the LVDS standard and strongly recommended for high-frequency drivers.
In accordance with again an added feature of the invention, the offset voltage is set to result in a voltage offset value between the first and second output terminals of approximately 1.2 V.
In accordance with again an additional feature of the invention, there is provided a voltage control circuit for regulating the offset voltage. Also, there may be provided a differential amplifier circuit having a voltage supply. In that case, the offset voltage is regulated by controlling the voltage supply to the differential amplifier.
In accordance with yet an added feature of the invention, there is provided a mirror circuit for setting a current through the first and second output terminals and a voltage between the first and second output terminals, the mirror circuit comprising two input terminals carrying respective reference voltages and the mirror circuit controlling the current source and the offset voltage such that a low level at one of the output terminals and a high level at another of the output terminals correspond to each of the reference voltages, respectively.
In accordance with yet a further feature of the invention, a high level of the output voltage is set with the regulated offset voltage. A low level of the output voltage is set with the current impressed by the current source.
The primary advantage achieved by the invention compared to the prior art is that the proposed electronic output stage can be driven with high-frequency small signals (<1V). This is advantageous particularly when amplifier circuits are integrated wherein small swings predominate.
Further advantages over the prior art are a reduced power loss and an ability to forgo the controlling of the current sources.
Another advantage of the electronic output stage compared to pure digital CMOS circuits is that there are no high-frequency voltage and current peaks which could interfere with the sensitive analog circuits. In the proposed circuit, a substantially constant current is generated in output drivers by the current sources. The transistors are driven in the saturated state.
Furthermore, interference is prevented by the reduced input swing.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an electronic output stage, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 4833423 (1989-05-01), Molloy
patent: 4859961 (1989-08-01), Davenport
patent: 5373249 (1994-12-01), Barrett, Jr. et al.
patent: 5451902 (1995-09-01), Huang et al.
patent: 5493253 (1996-02-01), Ogou
patent: 0 525 656 (1993-02-01), None
patent: 6303051 (1994-10-01), None
Laug “A high-current very wide-band tranconductance amplifier” IEEE Tranactions on Instrumentation and Measurement vol. 39, Issue 1, Feb. 1990 pp. 42-47.
Preisach H.: “Makrozellen für serielle Gbit/s Schnittstellen in 0.35 &mgr;m CMOS” [Makrocells For Serial Gbit/s Interfaces in 0,35 &mgr;m CMOS], Tag

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