Electronic multiplying and adding apparatus and method

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364760, G06F 752

Patent

active

055285295

ABSTRACT:
A multiply-accumulate circuit is described in which upon each multiply iteration some of the accumulate value bits are incorporated into the result with lower order subsequently non-changing bits being latched. In this way, a wide accumulate value can be dealt with without incurring a correspondingly wide data path through the multiply accumulate circuit. Initialisation of the multiply accumulate circuit with one of the carry value and save value as the first partial summand and the other as at least part of the accumulate value is performed to reduce the total number of iterative cycles required to produce the result.

REFERENCES:
patent: 5262976 (1993-11-01), Young et al.
patent: 5325320 (1994-06-01), Chiu
patent: 5426599 (1995-06-01), Machida

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