Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Patent
1993-07-29
1995-10-31
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
327194, 327220, 327403, H03K 17693
Patent
active
054633419
ABSTRACT:
An electric multiple-valued register for electrically maintaining a multiple-valued digital signal of a ternary value of (0, 1/2, 1), quaternary value of (0, 1/3, 2/3, 1) or quinternary value of (0, 1/4, 2/4, 3/4, 1) instead of a binary digital signal such that 1 digit is of 0 or 1 is realized by inserting an element having a stair shaped voltage-current characteristic into a coupling circuit of a conventional flip-flop circuit. It may be used for a quantization circuit with the aid of a step characteristic, a multivalued memory, a multivalued register, a multivalued loop memory, a multivalued pattern matching circuit, a voice recognition divide, pattern recognition device, or a associative memory device.
REFERENCES:
patent: 3155833 (1959-12-01), Fries
patent: 3292014 (1965-01-01), Brooksby
patent: 3849673 (1974-11-01), Koo
patent: 4438351 (1984-03-01), Schnermeyer
patent: 4442509 (1984-04-01), Herndon
patent: 4491745 (1985-01-01), Birch
patent: 4517475 (1985-05-01), Petty
patent: 4595999 (1986-05-01), Betirac
patent: 4780751 (1988-10-01), Nishimoto
patent: 4855617 (1989-08-01), Ovens
patent: 4883985 (1989-11-01), Katsu et al.
patent: 5043939 (1991-08-01), Stamowitz et al.
Sueo Tanaka et al; "An Analysis on the Phase Place of the Tristable Circuits"; Denshin Tsushin Gakkai, 69/11 vol. 52-C, pp. 667-674; 1969 and abridged translation thereof.
H. Arango et al., "Threshold Implementation of Ternary Systems", IEEE Transactions on Electronic Computers, EC-15, p. 661, Jan. 10, 1966, revised May 6, 1966.
Sueo Tanaka, et al, "An Analysis on the Phase Plane of the Tristable Circuits", Electron Communication Association Review '69/11, vol. 52-C, No. 11, UDC 621.373.52: 621.382.323, pp. 667-674, 1969.
Hisashi Mine, et al, "Tri-Stable Circuit Using FET", Electron Communication Association Review '68/11, vol. 51-C, No. 11, UDC 621.382.323: 621.374.3, pp. 532-533, 1968.
Shinji Karasawa et al; "Metal-Oxide-Semiconductor Field-Effect-Transistors Possessing Step Functional I-V Curves Caused by the Punch Through between Drain and Inversion Layer of the Gate"; Jpn. J. Appl. phys. vol. 31, pp. 217-224; Feb. 1992.
Shinji Karasawa et al; "Applications of a MOS Device with Stair Shaped I-V Curve"; International Conference on Advanced Microelectronic Devices and Processing; pp. 621-624.
Shinji Karasawa et al; "Design and Examination of a Multiple-Valued Flip-Flop Circuit with Stair Shaped I-V Curved Device as a Coupling Element"; IEEE Computer Society Press Reprint; pp. 152-157; 1993.
Callahan Timothy P.
Miyagi National College of Technology
Nu Ton My-Trang
LandOfFree
Electronic multiple-valued register does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic multiple-valued register, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic multiple-valued register will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1775999