Electronic modules with interconnected surface metallization lay

Details Electronic modules with interconnected surface metallization lay Electronic modules with interconnected surface metallization lay

1995-05-26

1996-05-14

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257698, 257700, 257723, 257730, 257777, H01L 2348, H01L 23538, H01L 23522

Patent

active

055170579

ABSTRACT:
Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.

REFERENCES:
patent: 4456694 (1990-09-01), Eide
patent: 5016138 (1991-05-01), Woodman
patent: 5107586 (1992-04-01), Eichelberger et al.
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5279029 (1994-01-01), Burns
patent: 5313096 (1994-05-01), Eide
patent: 5343075 (1994-08-01), Nishino
patent: 5377077 (1994-12-01), Burns

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