Electronic module having canopy-type carriers

Details Electronic module having canopy-type carriers Electronic module having canopy-type carriers

2000-10-16

2003-04-08

Thompson, Gregory (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C257S706000, C257S712000, C257S686000, C257S723000, C257S724000, C361S708000, C361S710000, C361S735000, C361S767000, C361S777000, C361S782000, C361S813000, C361S723000

Reexamination Certificate

active

06545868

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the production of multi-chip electronic modules, and more particularly to a method and apparatus for attaching multiple integrated circuit packages to printed circuit boards. It also relates to high-density memory modules having three-dimensional arrangements of integrated circuit packages.
BACKGROUND OF THE INVENTION
Demand for semiconductor memory is highly elastic. On one hand, when such memory is relatively inexpensive compared to the overall cost of a computer system, an almost unsatiable demand results, with computer manufacturers tending to install an amount of main memory in each system that greatly exceeds the amount required for average program use. On the other hand, when it is costly, manufacturers typically install an amount in each system that only marginally fulfills the requirement of the average program. Although the sales prices of computers may, thus, be maintained at low levels, the end user may soon find that he must upgrade his computer's main memory.
The ever increasing demand for large random access computer memories, and the growing demand for increasingly compact computers, coupled with an incentive on the part of the semiconductor manufacturers to reduce the cost per bit, has lead to not only a quadrupling of circuit density approximately every three years, but to increasingly efficient techniques for packaging and mounting the circuit chips. Up until the late 1980's, semiconductor memory chips were usually packaged as dual in-line pin packages (DlPPs). The pins of these DIPP packages were generally soldered directly within through-holes in a main circuit board (e.g., the motherboard), or they were inserted in sockets which were, in turn, soldered within through-holes in the main circuit board. With the advent of surface mount technology, conventional plated through-holes on printed circuit boards have been replaced with conductive mounting pads. Small Outline J-lead (SOJ) packages have lead to Thin Small Outline Packages (TSOPs).
Because the pitch or spacing between centers of adjacent surface mount pins is significantly less than the conventional 0.10-inch spacing for conventional through-hole components, surface mount chips tend to be considerably smaller than corresponding conventional chips, thus taking up less space on a printed circuit board. Additionally, as through holes are no longer needed, surface mount technology lends itself to the mounting of components on both sides of a printed circuit board. Memory modules utilizing surface-mount packages on both sides have become the standard. Both the earlier single in-line memory modules (SIMMs) and the currently used dual in-line memory modules (DIMMs) are inserted into sockets on the motherboard.
Packaging density may be increased rather dramatically by fabricating modules in which a plurality of integrated circuit (IC) chips, such as memory chips, are stacked in a three dimensional arrangement. As a general rule, the three-dimensional stacking of chips requires complex, non-standard packaging methods.
One example of a vertical stack of IC chips is provided by U.S. Pat. No. 4,956,694 to Floyd Eide, titled INTEGRATED CIRCUIT CHIP STACKING. A plurality of integrated circuits are packaged within package carriers and stacked, one on top of the other, on a printed circuit board. Except for the chip select terminal, all other like terminals on the chips are connected in parallel.
Another example of chip stacking is given in U.S. Pat. No. 5,128,831 to Fox, et al. titled HIGH-DENSITY ELECTRONIC PACKAGE COMPRISING STACKED SUB-MODULES WHICH ARE ELECTRICALLY INTERCONNECTED BY SOLDER-FILLED VIAS. The package is assembled from individually testable sub-modules, each of which has a single chip bonded thereto. The sub-modules are interleaved with frame-like spacers. Both the sub-modules and the spacers have alignable vias which provide interconnection between the various sub-modules.
U.S. Pat. No. 5,313,096, also issued to Floyd Eide and titled IC CHIP PACKAGE HAVING CHIP ATTACHED TO AND WIRE BONDED WITHIN AN OVERLYING SUBSTRATE, is another example. Such a package includes a chip having an upper active surface bonded to the lower surface of a lower substrate layer having conductive traces on its upper surface which terminate in conductive pads on its periphery. Connection between terminals on the active surface and the traces is made with wire bonds through apertures within the lower substrate layer. An upper substrate layer, which is bonded to the lower substrate layer, has apertures which coincide with those of the lower substrate layer and provide space in which the wire bonding may occur. After wire bonding has occurred, the apertures are filled with epoxy to form an individually testable sub-module. Multiple sub-modules can be stacked and interconnected with metal strips attached to their edges.
A final example of a stacked-chip module is disclosed in U.S. Pat. No. 5,869,353 to A. U. Levy, et al. titled MODULAR PANEL STACKING PROCESS. A plurality of panels are fabricated having apertures therein, an array of chip-mounting pads at the bottom of the apertures, and interfacing conductive pads. Both the chip-mounting pads and the interfacing conductive pads are coated with solder paste. Plastic-encapsulated surface-mount IC chips are positioned on the paste-covered mounting pads, multiple panels are stacked in a layered arrangement and the stack is heated to solder the chip leads to the mounting pads and the interfacing pads of adjacent panels together. Individual chip package stacks are then separated from the panel stack by a cutting and cleaving operation.
As can be seen by the foregoing examples, increased chip density is achieved through the use of complicated packaging and stacking arrangements, which must necessarily be reflected in a higher cost per bit of storage.
SUMMARY OF THE INVENTION
The present invention provides for increased circuit density on printed circuit boards. The invention, is particularly useful for increasing the density of memory chips on memory modules used for computer systems. The invention includes a package carrier that is designed to mount on a printed circuit board (PCB) on top of a first integrated circuit (IC) package that is also mounted on the PCB. The carrier has an upper major surface having a pad array on which a second IC package is mountable. When mounted on top of the first IC package, the carrier may be thought of as a canopy or platform, on top of which the second IC package is mounted. The carrier has a plurality of leads by means of which the carrier is surface mounted to the PCB. Each carrier lead is also electrically connected to a single pad of the pad array on the upper surface. The invention also includes a multi-chip module assembled using at least one PCB, at least one package carrier and at least two IC packages associated with each carrier (one mounted on the carrier and the other mounted beneath the carrier on the PCB). For multi-chip modules where the IC package beneath the carrier shares all or most connections in common with the IC package mounted thereupon, a single lead of the carrier and a single lead of the package beneath the carrier may share a mounting/connection pad on the PCB. When separate connections must be made by similarly positioned leads on the carrier and the package beneath the carrier, the corresponding pad on the PCB may be split so that each lead has a unique connection. Alternatively, a pad beneath an electrically unused lead on the lower package may be used for a unique signal for the upper package by rerouting the signal from the standard package lead to carrier lead which corresponds to the unused lead.
A first embodiment of the carrier includes a body having a first pad array, arranged as two parallel linear rows of pads, and adhered to an upper major surface thereof. The leads of an IC package may be conductively bonded to the pads of the first pad array. The body also has a second pad array, arranged as two parallel linear rows of pads positioned along the long

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